MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 114

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Phase-Lock Loop (PLL)
11.5.2 Reference Divider Registers
Read: Anytime
Write: Anytime
The count in the reference divider (RDV) 12-bit register divides the crystal oscillator clock input.
In the reset condition, both LDV and RDV are set to the maximum count which produces an internal
frequency at the phase detector of 8.2 kHz and a final output frequency of 16.8 MHz with a 16.8 MHz input
clock.
11.5.3 Clock Control Register
Read: Anytime
Write: Anytime
LCKF — Lock Flag
PLLON — PLL On Bit
114
This read-only flag is set when the PLL frequency is at least half the target frequency and no more than
twice the target frequency.
Setting PLLON turns on the PLL.
1 = PLL locked
0 = PLL not locked
1 = PLL on
0 = PLL off
Address: $0042
Address: $0043
Address: $0047
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
RDV7
LCKF
Bit 7
Bit 7
Bit 7
Figure 11-5. Reference Divider Register High (RDVH)
0
0
1
Figure 11-6. Reference Divider Register Low (RDVL)
0
Figure 11-7. Clock Control Register (CLKCTL)
= Unimplemented
= Unimplemented
PLLON
RDV6
6
0
0
6
1
6
0
MC68HC812A4 Data Sheet, Rev. 7
RDV5
PLLS
5
0
0
5
1
5
0
BCSC
RDV4
4
0
0
4
1
4
0
RDV11
RDV3
BCSB
3
1
3
1
3
0
RDV10
RDV2
BCSA
2
1
2
1
2
0
MCSB
RDV9
RDV1
1
1
1
1
1
0
Freescale Semiconductor
MCSA
RDV8
RDV0
Bit 0
Bit 0
Bit 0
1
1
0