MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 67

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.3.7 Port D Data Register
Read: Anytime, if register is in the map
Write: Anytime, if register is in the map
Bits PD7–PD0 correspond to data lines DATA7–DATA0. When port D is not used for external data, such
as in single-chip mode, these pins can be used as general-purpose I/O or key wakeup signals. DDRD
determines the primary direction of each port D pin.
In special expanded narrow mode, the external data bus is normally limited to eight bits on port C, but the
emulate port D bit (EMD) in the MODE register can be set to allow port C and port D to be used together
to provide single-cycle visibility of internal 16-bit accesses for debugging purposes. If the mode is special
narrow expanded and EMD is set, port D is configured for DATA7–DATA0 of visible internal accesses
and normal 16-bit external accesses are split into two adjacent 8-bit accesses through port C. This allows
connection of a single 8-bit external program memory.
This register is not in the on-chip map in wide expanded and peripheral modes. Also, in special narrow
expanded mode, the function of this port is determined by the EMD control bit. If EMD is set, this register
is not in the on-chip map and port D is used for DATA7–DATA0 of visible internal accesses. If EMD is
clear, this port serves as general-purpose I/O or key wakeup signals.
6.3.8 Port D Data Direction Register
Read: Anytime, if register is in the map
Write: Anytime, if register is in the map
When port D is operating as a general-purpose I/O port, this register determines the primary direction for
each port D pin.
This register is not in the map in wide expanded and peripheral modes. Also, in special narrow expanded
mode, the function of this port is determined by the EMD control bit. If EMD is set, this register is not in
the on-chip map and port D is used for DATA7–DATA0 of visible internal accesses. If EMD is clear, this
port serves as general-purpose I/O or key wakeup signals.
Freescale Semiconductor
Expanded wide and peripheral:
1 = Associated pin is an output.
0 = Associated pin is a high-impedance input.
Alternate pin function:
Address: $0007
Reset:
Read:
Write:
Address: $0005
Reset:
Read:
Write:
Bit 7
Bit 7
0
Figure 6-8. Port D Data Direction Register (DDRD)
DATA7
KWD7
Figure 6-7. Port D Data Register (PORTD)
Bit 7
PD7
0
Bit 6
6
0
MC68HC812A4 Data Sheet, Rev. 7
DATA6
KWD6
PD6
6
0
Bit 5
5
0
DATA5
KWD5
PD5
5
0
Bit 4
4
0
DATA4
KWD4
PD4
4
0
Bit 3
3
0
DATA3
KWD3
PD3
3
0
Bit 2
2
0
DATA2
KWD2
PD2
2
0
Bit 1
1
0
DATA1
KWD1
PD1
1
0
Bit 0
Bit 0
0
DATA0
KWD0
Bit 0
PD0
0
Registers
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