MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 158

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Serial Communications Interface Module (SCI)
register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI
control register 2 (SCCR2) is also set, the TDRE flag generates an SCI interrupt request.
When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1.
If at any time software clears the TE bit in SCI control register 2 (SCCR2), the transmitter and receiver
relinquish control of the port I/O pins.
If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register
continues to shift out. Then the TXD pin reverts to being a general-purpose I/O pin even if there is data
pending in the SCI data register. To avoid accidentally cutting off the last frame in a message, always wait
for TDRE to go high after the last frame before clearing TE.
To separate messages with preambles with minimum idle line time, use this sequence between
messages:
When the SCI relinquishes the TXD pin, the PORTS and DDRS registers control the TXD pin.
To force TXD high when turning off the transmitter, set bit 1 of the port S register (PORTS) and bit 1 of
the port S data direction register (DDRS). The TXD pin goes high as soon as the SCI relinquishes it.
14.5.3.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCCR2) loads the transmit shift
register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit.
Break character length depends on the M bit in SCI control register 1 (SCCR1). As long as SBK is at
logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software
clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at
least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the
start bit of the next frame.
The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a
logic 0 where the stop bit should be. Receiving a break character has these effects on SCI registers:
14.5.3.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends
on the M bit in SCI control register 1 (SCCR1). The preamble is a synchronizing idle character that begins
the first transmission initiated after writing the TE bit from 0 to 1.
If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the frame currently being transmitted.
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1. Write the last byte of the first message to SCDRH/L.
2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift
3. Queue a preamble by clearing and then setting the TE bit.
4. Write the first byte of the second message to SCDRH/L.
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register.
Sets the framing error flag, FE
Sets the receive data register full flag, RDRF
Clears the SCI data registers, SCDRH/L
May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF
(see
14.6.4 SCI Status Register
MC68HC812A4 Data Sheet, Rev. 7
1)
Freescale Semiconductor