MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 140

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Standard Timer Module
12.10.2 Timer Port Data Direction Register
Read: Anytime
Write: Anytime
Bits 7–0 — TIMPORT Data Direction Bits
The timer forces the I/O state to be an output for each timer port pin associated with an enabled output
compare. In these cases, the data direction bits do not change but have no effect on the direction of these
pins. The DDRT reverts to controlling the I/O direction of a pin when the associated timer output compare
is disabled. Input captures do not override the DDRT settings.
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These bits control the port logic of PORTT. Reset clears the timer port data direction register,
configuring all timer port pins as inputs.
1 = Corresponding pin configured as output
0 = Corresponding pin configured as input
Address: $00AF
Due to input synchronizer circuitry, the minimum pulse width for a pulse
accumulator input or an input capture input should always be greater than
the width of two module clocks.
By setting the IOSx bit input capture configuration no matter what the state
of the data direction register is, the timer forces output compare pins to be
outputs and input capture pins to be inputs.
Reset:
Data Direction
Read:
Write:
Register
0
0
1
1
Figure 12-26. Timer Port Data Direction Register (DDRT)
Bit 7
Bit 7
0
In
Output Compare
6
6
0
Table 12-6. TIMPORT I/O Function
Action
MC68HC812A4 Data Sheet, Rev. 7
0
1
1
0
5
5
0
NOTE
NOTE
Port data register
Port data register
4
4
0
at Data Bus
Reading
Pin
Pin
3
3
0
Out
2
2
0
Output compare action
Output compare action
Port data register
Reading at Pin
Pin
1
1
0
Freescale Semiconductor
Bit 0
Bit 0
0