21285-AB Unsupported Pci Cycles As Target - Intel Corporation
Manufacturer Part Number
Microprocessor, 21285 Core Logic For SA-110 Microprocessor
Specifications of 21285-AB
Note: Some master devices, such as Intel Semiconductor’s 21150, 21152, 21153, and 21154 PCI-to-PCI
Bridge chips, discard a transaction after 2
implies that the SA-110 should set the initialize complete bit before that time.
The following sections describe the target response of the 21285 to various PCI cycles.
Unsupported PCI Cycles As Target
The following PCI transactions are not supported by the 21285 as a target:
I/O write to SDRAM
I/O read to SDRAM
I/O write to ROM
I/O read to ROM
Type 1 configuration write
Type 1 configuration read
The following commands are aliased:
Memory write and invalidate to memory write
Memory read line and memory read multiple to memory read for CSR and ROM address space
only (that is, not SDRAM space)
Memory Write to SDRAM
PCI memory write to SDRAM occurs if the PCI address matches the SDRAM base address register
(at offset 18h) or the CSR base address register (at offset 10h with an offset greater than FFFh), and
the PCI command is either a memory write or a memory write and invalidate.
The PCI memory write data is collected in the Inbound FIFO and written to SDRAM at a later
time. The 21285 requests the SDRAM at the end of each eight Dword boundary of the PCI burst
(or at the end of the burst).
If PCI address bits [1:0] are not 00 (that is, not linear increment mode), and the master attempts to
continue the burst past the first Dword, the 21285 signals a target disconnect.
The PCI address is mapped down to local address 0 and then mapped up by the offset (see
21285 Core Logic for SA-110 Datasheet
retries. This takes approximately 1.9 seconds, which