21285-AB Type Configuration Write - Intel Corporation
Manufacturer Part Number
Microprocessor, 21285 Core Logic For SA-110 Microprocessor
Specifications of 21285-AB
If the delayed read latch is full and a new read to a different address is attempted, that read gets a
retry and no change is made in the delayed read latch. In other words, the new read does not
displace the in-progress read.
A memory read multiple command initiates streaming prefetch from SDRAM so that it can supply
read data at the maximum PCI bus data rate. Streaming prefetch works as follows:
The 21285 reads 32 Dwords when the read is initially queued. This means that the address
must be aligned to 32 Dwords.
When the PCI master repeats the read, the 21285 starts to deliver data. When the PCI master
consumes the 17th Dword, the 21285 reads the next 16 Dwords from SDRAM.
As long as the PCI master continues to consume the 16th Dword of subsequent blocks, the
21285 reads the next 16 Dwords.
The 21285 never stalls trdy_l while supplying SDRAM read data.
Streaming prefetch does not start if a PCI write to SDRAM or ROM is queued into the Inbound
FIFO between the delayed read being started and the read data being delivered. This allows the
write data to be written to SDRAM. In this case, only the first 32 Dwords are read.
Streaming prefetch stops when any of the following events occur:
The address crosses a SDRAM page boundary.
The PCI master ends the cycle (by deasserting frame_l). In this case, the 21285 discards any
remaining prefetched data immediately.
Other bus activity on the SA-110 bus prevents data from being available in time; the 21285
will never negate trdy_l for the burst
Type 0 Configuration Write
PCI configuration write to the CSR occurs when idsel is asserted, the PCI command is a
configuration write, and the PCI address bits [1:0] are 00. The PCI write data is written to the CSR
selected by PCI address bits [7:2]. The PCI byte enables determine which bytes are written. If a
nonexistent CSR is selected within the CSR address range, the data is discarded and no error action
If the PCI master attempts to do a burst longer than one data phase, the 21285 target disconnects.
Type 0 Configuration Read
PCI configuration read to the CSR occurs when idsel is asserted, the PCI command is a
configuration read, and the PCI address bits [1:0] are 00. The data from the CSR selected by PCI
address bits [7:2] is returned on ad[31:0]. If a nonexistent CSR is selected within the CSR address
range, the data returned is zeros and no error action is taken.
If the PCI master attempts to do a burst longer than one data phase, the 21285 target disconnects
21285 Core Logic for SA-110 Datasheet