21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 

Specifications of 21285-AB

CaseBGADc99+/00+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Page 41
42
Page 42
43
Page 43
44
Page 44
45
Page 45
46
Page 46
47
Page 47
48
Page 48
49
Page 49
50
Page 50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
Page 44/159:

Type Configuration Write

Download datasheet (780Kb)Embed
PrevNext
Transactions
If the delayed read latch is full and a new read to a different address is attempted, that read gets a
retry and no change is made in the delayed read latch. In other words, the new read does not
displace the in-progress read.
A memory read multiple command initiates streaming prefetch from SDRAM so that it can supply
read data at the maximum PCI bus data rate. Streaming prefetch works as follows:
The 21285 reads 32 Dwords when the read is initially queued. This means that the address
must be aligned to 32 Dwords.
When the PCI master repeats the read, the 21285 starts to deliver data. When the PCI master
consumes the 17th Dword, the 21285 reads the next 16 Dwords from SDRAM.
As long as the PCI master continues to consume the 16th Dword of subsequent blocks, the
21285 reads the next 16 Dwords.
The 21285 never stalls trdy_l while supplying SDRAM read data.
Streaming prefetch does not start if a PCI write to SDRAM or ROM is queued into the Inbound
FIFO between the delayed read being started and the read data being delivered. This allows the
write data to be written to SDRAM. In this case, only the first 32 Dwords are read.
Streaming prefetch stops when any of the following events occur:
The address crosses a SDRAM page boundary.
The PCI master ends the cycle (by deasserting frame_l). In this case, the 21285 discards any
remaining prefetched data immediately.
Other bus activity on the SA-110 bus prevents data from being available in time; the 21285
will never negate trdy_l for the burst
3.2.4
Type 0 Configuration Write
PCI configuration write to the CSR occurs when idsel is asserted, the PCI command is a
configuration write, and the PCI address bits [1:0] are 00. The PCI write data is written to the CSR
selected by PCI address bits [7:2]. The PCI byte enables determine which bytes are written. If a
nonexistent CSR is selected within the CSR address range, the data is discarded and no error action
is taken.
If the PCI master attempts to do a burst longer than one data phase, the 21285 target disconnects.
3.2.5
Type 0 Configuration Read
PCI configuration read to the CSR occurs when idsel is asserted, the PCI command is a
configuration read, and the PCI address bits [1:0] are 00. The data from the CSR selected by PCI
address bits [7:2] is returned on ad[31:0]. If a nonexistent CSR is selected within the CSR address
range, the data returned is zeros and no error action is taken.
If the PCI master attempts to do a burst longer than one data phase, the 21285 target disconnects
.
3-10
21285 Core Logic for SA-110 Datasheet