MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet
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... Freescale Semiconductor, Inc. MC68F375 REFERENCE MANUAL Revised 25 June 2003 Copyright 2003 MOTOROLA; All Rights Reserved For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. MC68F375 REFERENCE MANUAL Revised 25 June 2003 Copyright 2003 MOTOROLA; All Rights Reserved For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Number OVERVIEW DESCRIPTION 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 MC68F375 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.3 Module Descriptions 1-3 1.3.1 Central Processing Unit Module – CPU32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3.2 Single Chip Integration Module – SCIM2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3.3 Queued Analog to Digital Converter Module – QADC64 . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3.4 Analog Multiplexer – ...
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... Freescale Semiconductor, Inc. Paragraph Number 3.2.5 Vector Base Register (VBR 3-7 3.3 Memory Organization 3-7 3.4 Virtual Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.6 Processing States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.7 Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.8 Instructions 3-10 3.8.1 M68000 Family Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.8.2 Special Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3 ...
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... Freescale Semiconductor, Inc. Paragraph Number 4.2.3 Interrupt Arbitration 4-4 4.2.4 Noise Reduction in Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.5 Show Internal Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.6 FREEZE Assertion Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.1 System Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.2 Clock Synthesizer Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.3 Slow Reference Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4 ...
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... Freescale Semiconductor, Inc. Paragraph Number 4.4.9 Low Power Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4.4.9.1 Periodic Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4.4.9.2 Periodic Interrupt Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 4.5 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 4.5.1 Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 4.5.1.1 Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 4.5.1.2 Address Strobe 4-32 4 ...
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... Freescale Semiconductor, Inc. Paragraph Number 4.7.6 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57 4.7.7 Pin State During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58 4.7.7.1 Reset States of SCIM2E Pins 4-58 4.7.7.2 Reset States of Pins Assigned to Other MCU Modules . . . . . . . . . . . . . . . . . . . . . 4-59 4.7.8 Operating Configuration Out of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60 4.7.8.1 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60 4 ...
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... Freescale Semiconductor, Inc. Paragraph Number QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 QADC64 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3.1 Port A Pin Functions 5-4 5.3.1.1 Port A Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.3.1.2 Port A Digital Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.3.2 Port B Pin Functions 5-4 5 ...
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... Freescale Semiconductor, Inc. Paragraph Number 5.10.4 QADC64 Clock (QCLK) Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.10.5 Periodic/Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.11 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.11.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5.11.1.1 Polled and Interrupt-Driven Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5.11.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5.11.3 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.11.4 Interrupt Arbitration 5-31 5.11.5 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 5 ...
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... Freescale Semiconductor, Inc. Paragraph Number 6.6.1 Port QS Data Register (PORTQS 6-10 6.6.2 PORTQS Pin Assignment Register (PQSPAR 6-10 6.6.3 PORTQS Data Direction Register (DDRQS 6-12 6.7 Queued Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.7.1 QSPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.7.1.1 QSPI Control Register 6-16 6.7.1.2 QSPI Control Register 6-18 6 ...
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... Freescale Semiconductor, Inc. Paragraph Number 6.8.7.5 Transmitter Operation 6-52 6.8.7.6 Receiver Operation 6-54 6.8.7.7 Idle-Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 6.8.7.8 Receiver Wake- 6-56 6.8.7.9 Internal Loop Mode 6-57 6.9 SCI Queue Operation 6-57 6.9.1 Queue Operation of SCI1 for Transmit and Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57 6.9.2 Queued SCI1 Status and Control Registers 6-57 6 ...
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... Freescale Semiconductor, Inc. Paragraph Number 7.5.3.1 Transmit Message Buffer Deactivation 7-13 7.5.3.2 Reception of Transmitted Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.5.4 Receive Process 7-13 7.5.4.1 Receive Message Buffer Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.5.4.2 Locking and Releasing Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.5.5 Remote Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7.5.6 Overload Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7 ...
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... Freescale Semiconductor, Inc. Paragraph Number 8.3.5 Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.6 Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.7 TPU3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.3.8 Prescaler Control for TCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.3.9 Prescaler Control for TCR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.4 Programming Model 8-8 8.4.1 TPU Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.4.2 TPU3 Test Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8 ...
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... Freescale Semiconductor, Inc. Paragraph Number 9.5.6 TPU3 Emulation Mode Operation 9-7 9.6 Multiple Input Signature Calculator (MISC 9-8 CDR MoneT FLASH FOR THE IMB3 (CMFI) 10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.1 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.2 Features of the CMFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.1.3 Glossary of terms used in the CMFI EEPROM Specification . . . . . . . . . . . . . . . . . . . . 10-4 10 ...
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... Freescale Semiconductor, Inc. Paragraph Number 10.6.9 Background Debug Mode or Freeze Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35 STATIC RANDOM ACCESS MEMORY (SRAM) 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2.1 SRAM Control Block 11-1 11.2.2 SRAM Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2.2.1 SRAM Array Addressing 11-3 11.3 SRAM Module Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11 ...
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... Freescale Semiconductor, Inc. Paragraph Number CONFIGURABLE TIMER MODULE (CTM9) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1.1 CTM9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1.2 CTM9 Pins and Naming Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.2 Free Running Counter Submodule (FCSM 13-4 13.2.1 The FCSM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.2.2 FCSM Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.2.3 FCSM External Event Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13 ...
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... Freescale Semiconductor, Inc. Paragraph Number 13.5 Double-Action Submodule (DASM 13-23 13.5.1 32-Bit Coherent Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25 13.5.2 DASM Modes of Operation 13-25 13.5.2.1 Disable (DIS) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26 13.5.2.2 Input Pulse Width Measurement (IPWM) Mode . . . . . . . . . . . . . . . . . . . . . . . . . 13-26 13.5.2.3 Input Period Measurement (IPM) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-27 13.5.2.4 Input Capture (IC) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28 13 ...
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... Freescale Semiconductor, Inc. Paragraph Number 13.9.1 Freeze Action on the CPSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-53 13.9.2 CPSM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-53 13.9.2.1 CPCR — CPSM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-54 13.9.3 Clock Sources for the Counter Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-54 13.10 CTM9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-55 13.11 CTM9 Function Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-55 13.11.1 CTM9 Single Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-55 13 ...
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... Freescale Semiconductor, Inc. Paragraph Number D.17.2 Host CPU Initialization of the SIOP Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-45 D.17.3 SIOP Function Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-45 D.17.3.1 XFER_SIZE Greater than D-46 D.17.3.2 Data Positioning D-46 D.17.3.3 Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-46 ELECTRICAL CHARACTERISTICS E.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 E.2 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 E ...
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... Freescale Semiconductor, Inc. Paragraph Number MC68F375 REFERENCE MANUAL For More Information On This Product, TABLE OF CONTENTS Rev. 25 June 03 Go to: www.freescale.com Page Number MOTOROLA xx ...
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... Freescale Semiconductor, Inc. LIST OF FIGURES Figure Number 1-1 MC68F375 Block Diagram ............................................................................. 1-7 1-2 MC68F375 Address Map .............................................................................. 1-10 2-1 MC68F375 Pad Map ...................................................................................... 2-8 2-2 MC68F375 Ball Map ....................................................................................... 2-9 3-1 CPU32 Block Diagram .................................................................................... 3-2 3-2 User Programming Model ............................................................................... 3-3 3-3 Supervisor Programming Model Supplement ................................................. 3-4 3-4 Data Organization in Data Registers ...
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... Freescale Semiconductor, Inc. Figure Number 5-1 QADC64 Block Diagram ................................................................................. 5-1 5-2 QADC64 Input and Output Signals ................................................................. 5-3 5-3 Example of Full External Multiplexing ........................................................... 5-10 5-4 QADC64 Module Block Diagram .................................................................. 5-12 5-5 Conversion Timing ........................................................................................ 5-13 5-6 Bypass Mode Conversion Timing ................................................................. 5-13 5-7 QADC64 Queue Operation with Pause ........................................................ 5-16 5-8 QADC64 Clock Subsystem Functions ...
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... Freescale Semiconductor, Inc. Figure Number 9-1 DPTRAM Configuration .................................................................................. 9-2 10-1 Block Diagram for a CMFI EEPROM in the 256-Kbyte Configuration. ......... 10-2 10-3 Shadow Information .................................................................................... 10-12 10-2 10-4 Pulse Status Timing .................................................................................... 10-19 10-5 Master Reset Configuration Timing ............................................................ 10-24 10-6 Program State Diagram .............................................................................. 10-28 10-7 Erase State Diagram ...
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... Freescale Semiconductor, Inc. Figure Number D-14 MCPWM Parameters — Slave Edge-Aligned Mode ....................................D-23 D-15 MCPWM Parameters — Slave Ch A Non-Inverted Center-Aligned Mode ...D-24 D-16 MCPWM Parameters — Slave Ch B Non-Inverted Center-Aligned Mode ...D-25 D-17 MCPWM Parameters — Slave Ch A Inverted Center-Aligned Mode ...........D-26 D-18 MCPWM Parameters — ...
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... Freescale Semiconductor, Inc. LIST OF TABLES Table Number 1-1 MC68F375 Pin Usage .......................................................................................... 1-8 2-1 Pin Characteristics................................................................................................. 2-1 2-2 Power Connections................................................................................................ 2-3 2-3 Output Driver Types............................................................................................... 2-4 2-4 Signal Characteristics ............................................................................................ 2-4 2-5 Signal Functions .................................................................................................... 2-6 3-1 Unimplemented MC68020 Instructions................................................................ 3-10 3-2 Instruction Set Summary ..................................................................................... 3-11 3-3 Exception Vector Assignments ...
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... Freescale Semiconductor, Inc. Table Number 4-28 Reset Pin Function of CS[10:6] ......................................................................... 4-67 4-29 Reset Configuration for MC68F375 Memory Modules ...................................... 4-67 4-30 Partially (8-bit) Expanded Mode Reset Configuration........................................ 4-68 4-31 CSPAR0 Pin Assignments................................................................................. 4-76 4-32 CSPAR1 Pin Assignments................................................................................. 4-77 4-33 Reset Pin Function of CS[10:6] ......................................................................... 4-77 4-34 Pin Assignment Field Encoding ...
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... Freescale Semiconductor, Inc. Table Number 6-3 QSMCMMCR Bit Settings...................................................................................... 6-7 6-4 QILR Bit Settings ................................................................................................... 6-8 6-5 QIVR Bit Settings................................................................................................... 6-8 6-6 QSPI_IL Bit Settings .............................................................................................. 6-8 6-7 QSMCM Pin Control Registers .............................................................................. 6-9 6-8 Effect of DDRQS on QSPI Pin Function .............................................................. 6-10 6-9 QSMCM Pin Functions ........................................................................................ 6-11 6-10 PQSPAR Bit Settings ...
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... Freescale Semiconductor, Inc. Table Number 7-15 Transmit Pin Configuration ................................................................................ 7-27 7-16 CANCTRL1 Bit Settings..................................................................................... 7-28 7-17 PRESDIV Bit Settings....................................................................................... 7-29 7-18 CANCTRL2 Bit Settings.................................................................................... 7-29 7-19 TIMER Bit Settings ........................................................................................... 7-30 7-20 RXGMSKHI, RXGMSKLO Bit Settings ............................................................. 7-30 7-21 ESTAT Bit Settings ........................................................................................... 7-31 7-22 Transmit Bit Error Status ...
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... Freescale Semiconductor, Inc. Table Number 10-7 CMF Erase Algorithm (v6) ............................................................................... 10-14 10-8 CMFIBAR (CMFIBAH, CMFIBAL) Bit Settings ................................................ 10-15 10-9 CMFICTL1 Bit Settings .................................................................................... 10-16 10-10 CMFICTL2 Bit Settings.................................................................................. 10-17 10-11 System Clock Range ..................................................................................... 10-20 10-12 Clock Period Exponent and Pulse Width Range ........................................... 10-21 10-13 Program Interlock State Descriptions ...
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... Freescale Semiconductor, Inc. Table Number 13-21 CPCR Bit Settings ......................................................................................... 13-54 13-22 Prescaler Division Ratio Select...................................................................... 13-54 A-1 TouCAN (CAN 2.0B Controller)............................................................................. A-2 A-2 CTM9 (Configurable Timer Module)...................................................................... A-4 A-3 QADC64 (Queued Analog-to-Digital Converter) ................................................... A-7 A-4 CMFI (CDR MoneT FLASH FOR THE IMB3) ....................................................... A-8 A-5 ROM Module ...
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... Freescale Semiconductor, Inc. Table Number E-26 CMFI AC and DC Power Supply Characteristics .............................................. E-33 E-27 CMFI FLASH EEPROM Module Life................................................................. E-34 E-28 IMB3 ROM AC/DC Characteristics.................................................................... E-36 MC68F375 REFERENCE MANUAL For More Information On This Product, LIST OF TABLES Rev. 25 June 03 Go to: www.freescale.com Page Number ...
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... Freescale Semiconductor, Inc. Table Number MC68F375 REFERENCE MANUAL For More Information On This Product, LIST OF TABLES Rev. 25 June 03 Go to: www.freescale.com Page Number MOTOROLA xxxii ...
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... Freescale Semiconductor, Inc. This manual describes the capabilities, operation, and functions of the MC68F375 microcontroller unit. Documentation for the Modular Microcontroller Family follows the modular construction of the devices in the product line. Each device has a com- prehensive user’s manual which provides sufficient information for normal opera- tion of the device. The user’ ...
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... Freescale Semiconductor, Inc. The following conventions are used throughout the manual. Logic level one is the voltage that corresponds to a Boolean true (1) state. Logic level zero is the voltage that corresponds to a Boolean false (0) state. To set a bit means to establish logic level one on the bit. ...
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... Freescale Semiconductor, Inc. OVERVIEW DESCRIPTION 1.1 Introduction The MC68F375 is a member of the MC68300/68HC16 family of modular microcontrol- lers. This family includes a series of modules from which numerous microcontrollers (MCU’s) are derived. These modules are connected on-chip via the intermodule bus (IMB). This section includes a list of pins that are available to each module on the chip, ...
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... Freescale Semiconductor, Inc. — Dual function I/O port pins. • Time processing unit (TPU3): — 16 channels – each is associated with a pin. — Each channel can perform any time function. — Each time function may be assigned to more than one channel. — Each channel has an event register comprised of: 16-bit capture register, 16- bit compare/match register, 16-bit greater-than-or-equal-to comparator. — ...
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... Freescale Semiconductor, Inc. — 2 modulus counter submodules (MCSM). — 4 single action submodules (SASM). — 4 double action submodules (DASM). — 4 dedicated PWM submodules (PWMSM) • Package: flip chip and 217-ball PBGA. • Operating temperature: -40 C through 125 C • Operating frequency: 33.00 MHz system clock ...
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... Freescale Semiconductor, Inc. • The port logic provides input-only and 8 bidirectional digital interface pins. Pins which are used as analog channels should be masked out of the digital data. 1.3.4 Analog Multiplexer – AMUX The analog multiplexer (AMUX) submodule expands the channel capacity of the QADC64 analog-to-digital converter inputs by a maximum of 32 analog channels ...
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... Freescale Semiconductor, Inc. functions replace software functions that would require host CPU interrupt service. Re- fer to SECTION 8 TIME PROCESSOR UNIT 1.3.8 DPTRAM TPU Emulation RAM Module – DPTRAM The RAM module with TPU microcode storage support (DPTRAM) consists of a con- trol register block and a 6-Kbyte array of static RAM which can be used as a microcode storage for TPU3 or general purpose memory ...
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... Freescale Semiconductor, Inc. 1, the STOP bit in the ROMMCR register will be cleared to 0 and the array will respond normally to the bootstrap address range and the ROM array base address. If DATA14 is 0, the STOP bit will be set and the bootstrap address range and the ROM array will be disabled until the STOP bit is cleared either by an IMB write or until the next master reset which occurs with DATA14 = 1 ...
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... Freescale Semiconductor, Inc. 1.5 MC68F375 Functional Block Diagram Port CT QADC64 CTM9 w/ AMUX 1 FCSM 2 MCSM 4 SASM 4 DASM 4 PWMSM Intermodule Bus (IMB3) TouCAN ECK* RXD[1,2] TXD[1,2] PCS0/SS PCS1 PCS2 PCS3 SCK MISO MOSI Figure 1-1 MC68F375 Block Diagram MC68F375 REFERENCE MANUAL For More Information On This Product, ...
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... Freescale Semiconductor, Inc. 1.6 MC68F375 Pin Usage Table 1-1 shows the MC68F375 pin usage. For more information on an individual pin, refer to the corresponding module documentation. Table 1-1 MC68F375 Pin Usage Functions CPU32 BDM Total SCIM2E Port A, Port B Port G, Port H Port F Port C ...
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... Freescale Semiconductor, Inc. Table 1-1 MC68F375 Pin Usage (Continued) Functions Power ( DDH DDL I/O Pad Power (V DDH Logic Power (V ) DDL Ground ( SRAM (V ) STBY DPTRAM (V DDDPTRAM CMFI ( SCIM2E Clock (V DDSYN QADC64 Power (V DDA QADC64 Reference (V Total 1.7 Address Map Each MC68300/MC68HC16 derivative MCU has a 4-Kbyte block in the memory map that is assigned to internal module registers ...
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... Freescale Semiconductor, Inc. 0xYF F000 Unused 0xYF F080 TouCAN 384 Bytes 0xYF F200 CTM9 256 Bytes 0xYF F300 Unused 0xYF F400 QADC64 1024 Bytes 0xYF F800 256K CMFI CTL, 32 Bytes 0xYF F820 ROM CTL, 32 Bytes 0xYF F840 OVERLAY SRAM1 CTL, 8 Bytes ...
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... Freescale Semiconductor, Inc. SIGNAL DESCRIPTIONS 2.1 Pin Characteristics Table 2-1 shows MCU pins and their characteristics. All inputs detect CMOS logic lev- els. All inputs can be put in a high impedance state, but the method of doing this differs depending upon pin function. Refer to entry in the discrete I/O column of the MC68F375 pin characteristics table indicates that a pin has an alternate I/O function ...
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... Freescale Semiconductor, Inc. Table 2-1 Pin Characteristics (Continued) Pin Mnemonic Module CPWM[8:5] CTM9 CTD[10:9] CTM9 CTM2C CTM9 CTS[20B-14A] CTM9 DATA[15:8]/PG[7:0] SCIM2E DATA[7:0]/PH[7:0] SCIM2E DS/PE[4] SCIM2E DSACK[1:0]/PE[1:0] SCIM2E ETRIG[2:1]/PQA[4:3] QADC64 4,5 PLLWXY EXTAL 6 SCIM2E FASTREF/PF[0] FC[2]/CS[5]/PC[2] ...
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... Freescale Semiconductor, Inc. Table 2-1 Pin Characteristics (Continued) Pin Mnemonic Module 3 CMFI EPEB0 4 PLLWXY XFC 4,3 PLLWXY XTAL NOTES: 1. DATA[15:0] 2. DATA[15:0] 3. DATA[15:0] 4. EXTAL, XFC and XTAL are clock reference connections. 5. These pins are 3 V level only. 6. All Port F pins have weak pull-up. ...
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... Freescale Semiconductor, Inc. Table 2-3 Output Driver Types Type I Output that is always driven. No external pull-up required. Aqa O Type A output open drain on a QADC64 pin Three-state output that includes circuitry to assert output before high impedance is estab lished, to ensure rapid rise time. An external holding resistor is required to maintain logic level while in the high-impedance state ...
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... Freescale Semiconductor, Inc. Table 2-4 Signal Characteristics (Continued) Signal Name ETRIG[2:1] 1 EXTAL FASTREF FC[2]/CS[5]/PC[2] FC[1]/PC[1] FC[0]/CS[3]/PC[0] FREEZE HALT IPIPE IFETCH IRQ[7:1] MA[2:0] MISO MOSI PCS[3:0] PQA[7:0] PQB[7:0] QUOT R/W RESET RMC RXD1, RXD2 SCK SIZ[1:0] SS T2CLK ...
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... Freescale Semiconductor, Inc. Signal Name Mnemonic Address Bus ADDR[23:0] QADC64 Analog Input AN[59:48]/[3:0] QADC64 Analog Input AN[ Analog MUX Inputs ANX[15:0] Address Strobe AS Autovector AVEC Bus Error BERR Bus Grant BG Bus Grant Acknowledge BGACK Breakpoint BKPT Bus Request BR System Clock Out ...
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... Freescale Semiconductor, Inc. Table 2-5 Signal Functions (Continued) Signal Name Mnemonic Instruction Pipeline IFETCH Interrupt Request Level IRQ[7:1] QADC64 Multiplexed Ad- MA[2:0] dress Master-In Slave-Out MISO Master-Out Slave-In MOSI Peripheral Chip Select PCS[3:0] QADC64 Port A PQA[7:0] QADC64 Port B PQB[7:0] Quotient Out QUOT ...
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... Freescale Semiconductor, Inc. ANX15 ANX14 ANX13 ANX12 ANX11 ANX10 ANX9 QADC64 ANX8 ANX7 w/ AMUX ANX6 ANX5 ANX4 ANX3 ANX2 ANX1 ANX0 VRL VRH VSSA VDDA VPP EPEB0 VSTBY VSS VDDH ADDR18/PA7 ADDR17/PA6 ADDR16/PA5 ADDR15/PA4 ADDR14/PA3 ADDR13/PA2 ADDR12/PA1 ADDR11/PA0 ADDR10/PB7 ADDR9/PB6 VSS ...
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... Freescale Semiconductor, Inc. Note: N CONNECTION — these balls have no electrical connection inside the package. Figure 2-2 MC68F375 Ball Map MC68F375 REFERENCE MANUAL For More Information On This Product, SIGNAL DESCRIPTIONS Rev. 25 June 03 Go to: www.freescale.com MOTOROLA 2-9 ...
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... Freescale Semiconductor, Inc. MC68F375 REFERENCE MANUAL For More Information On This Product, SIGNAL DESCRIPTIONS Rev. 25 June 03 Go to: www.freescale.com MOTOROLA 2-10 ...
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... Freescale Semiconductor, Inc. CENTRAL PROCESSOR UNIT The CPU32, the instruction processing module of the M68300 family, is based on the industry-standard MC68000 processor. It has many features of the MC68010 and MC68020, as well as unique features suited for high-performance controller applica- tions. This section is an overview of the CPU32. For detailed information concerning CPU operation, refer to the 3 ...
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... Freescale Semiconductor, Inc. CONTROL STORE CONTROL LOGIC MICROSEQUENCER AND CONTROL ADDRESS Figure 3-1 CPU32 Block Diagram 3.2 CPU32 Registers The CPU32 programming model consists of two groups of registers that correspond to the user and supervisor privilege levels. User programs can use only the registers of the user model ...
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... Freescale Semiconductor, Inc Figure 3-2 User Programming Model MC68F375 REFERENCE MANUAL For More Information On This Product A7’ (USP) USER STACK POINTER CCR CONDITION CODE REGISTER CENTRAL PROCESSOR UNIT Rev. 25 June 03 Go to: www.freescale.com DATA REGISTERS ADDRESS REGISTERS PROGRAM COUNTER CPU32 USER PROG MODEL ...
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... Freescale Semiconductor, Inc Figure 3-3 Supervisor Programming Model Supplement 3.2.1 Data Registers The eight data registers can store data operands 16, 32, and 64 bits and addresses bits. The following data types are supported: • Bits • Packed Binary-Coded Decimal Digits • Byte Integers (8 bits) • ...
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... Freescale Semiconductor, Inc MSB HIGH-ORDER BYTE MIDDLE HIGH BYTE MIDDLE LOW BYTE LOW-ORDER BYTE 31 HIGH-ORDER WORD MSB 31 LOW-ORDER LONG WORD Figure 3-4 Data Organization in Data Registers 3.2.2 Address Registers Each address register and stack pointer is 32 bits wide and holds a 32-bit address. ...
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... Freescale Semiconductor, Inc. 31 SIGN EXTENDED 31 FULL 32-BIT ADDRESS OPERAND Figure 3-5 Address Organization in Address Registers 3.2.3 Program Counter The PC contains the address of the next instruction to be executed by the CPU32. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC as appropriate. ...
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... Freescale Semiconductor, Inc. 3.2.4.2 Alternate Function Code Registers Alternate function code registers (SFC and DFC) contain 3-bit function codes. Func- tion codes can be considered extensions of the 24-bit linear address that optionally provide as many as eight 16-Mbyte address spaces. The processor automatically gen- ...
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... Freescale Semiconductor, Inc MSB BYTE 0 BYTE 2 15 MSB 15 MSB LONG WORD 0 LONG WORD 1 LONG WORD 2 15 MSB ADDRESS 0 ADDRESS 1 ADDRESS 2 MSB = Most Significant Bit LSB = Least Significant Bit MSD BCD 0 BCD 4 MSD = Most Significant Digit LSD = Least Significant Digit Figure 3-6 Memory Operand Addressing ...
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... Freescale Semiconductor, Inc. 3.4 Virtual Memory The full addressing range of the CPU32 on the MC68F375 is 16 Mbytes in each of eight address spaces. Even though most systems implement a smaller physical mem- ory, the system can be made to appear to have a full 16 Mbytes of memory available to each user program by using virtual memory techniques. ...
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... Freescale Semiconductor, Inc. tion. Exception processing can be forced externally by an interrupt, a bus error reset. The background processing state is initiated by breakpoints, execution of special instructions double bus fault. Background processing is enabled by pulling BKPT low during RESET. Background processing allows interactive debugging of the sys- tem via a simple serial interface ...
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... Freescale Semiconductor, Inc. Table 3-2 Instruction Set Summary Operand Operand Instruction Syntax Size Dn, Dn ABCD (An), (An) Dn, <ea> 8, 16, 32 ADD <ea> 16, 32 ADDA <ea>, An 16, 32 #<data>, ADDI 8, 16, 32 <ea> # <data>, ADDQ 8, 16, 32 <ea> Dn 16, 32 ADDX (An), (An) 8, 16, 32 <ea> 16, 32 AND Dn, <ea> < ...
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... Freescale Semiconductor, Inc. Table 3-2 Instruction Set Summary (Continued) Operand Operand Instruction Syntax Size CMP <ea> 16, 32 CMPA <ea> <data>, CMPI 8, 16, 32 <ea> CMPM (An) , (An) 8, 16, 32 CMP2 <ea> 16, 32 DBcc Dn, label 32/16 DIVS/DIVU <ea>, Dn 64/32 <ea> DIVSL/DIVUL <ea>, Dq 32/32 <ea> ...
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... Freescale Semiconductor, Inc. Table 3-2 Instruction Set Summary (Continued) Operand Operand Instruction Syntax Size MOVE from SR, <ea> <ea>, SR MOVE to SR USP MOVE USP An, USP Rc MOVEC Rn, Rc list, <ea> 16, 32 MOVEM <ea>, list 16, 32 Dn, (d16, An) MOVEP 16, 32 (d16, An), Dn MOVEQ #<data> Rn, <ea> ...
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... Freescale Semiconductor, Inc. Table 3-2 Instruction Set Summary (Continued) Operand Operand Instruction Syntax Size 1 none none RTE RTR none none RTS none none Dn, Dn SBCD (An), (An) Scc <ea> 1 #<data> STOP <ea>, Dn SUB 8, 16, 32 Dn, <ea> SUBA <ea>, An 16, 32 #<data>, SUBI 8, 16, 32 < ...
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... Freescale Semiconductor, Inc. 3.8.1 M68000 Family Compatibility It is the philosophy of the M68000 family that all user-mode programs can execute unchanged on future derivatives of the M68000 family. Supervisor-mode programs and exception handlers should require only minimal alteration. The CPU32 can be thought intermediate member of the M68000 Family. ...
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... Freescale Semiconductor, Inc. Figure 3-7 Loop Mode Instruction Sequence The loop mode is entered when the DBcc instruction is executed, and the loop dis- placement is –4. Once in loop mode, the processor performs only the data cycles associated with the instruction and suppresses all instruction fetches. The termination condition and count are checked after each execution of the data operations of the looped instruction ...
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... Freescale Semiconductor, Inc. Table 3-3 Exception Vector Assignments Vector Number Dec 16– 100 26 104 27 108 28 112 29 116 30 120 31 124 128 32–47 188 192 48–58 232 236 59–63 252 256 64–255 1020 Each vector is assigned an 8-bit number. Vector numbers for some exceptions are obtained from an external device ...
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... Freescale Semiconductor, Inc. 3.9.2 Types of Exceptions An exception can be caused by internal or external events. An internal exception can be generated by an instruction error. The TRAP, TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause excep- tions during normal execution. Illegal instructions, instruction fetches from odd addresses, word or long-word operand accesses from odd addresses, and privilege violations also cause internal exceptions ...
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... Freescale Semiconductor, Inc. • Hardware Breakpoints 3.10.1 M68000 Family Development Support All M68000 Family members include features to facilitate applications development. These features include the following: Trace on Instruction Execution — M68000 Family processors include an instruction- by-instruction tracing facility as an aid to program development. The MC68020, MC68030, MC68040, and CPU32 also allow tracing only of those instructions causing a change in program flow ...
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... Freescale Semiconductor, Inc. TARGET SYSTEM Figure 3-8 Common In-Circuit Emulator Diagram TARGET SYSTEM TARGET MCU Figure 3-9 Bus State Analyzer Configuration 3.10.3 Enabling BDM Accidentally entering BDM in a non-development environment can lock up the CPU32 when the serial command interface is not available. For this reason, BDM is enabled during reset via the breakpoint (BKPT) signal ...
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... Freescale Semiconductor, Inc. Table 3-4 summarizes the processing of each source for both enabled and disabled cases. As shown in Table BDM. Table 3-4 BDM Source Summary Source BKPT Double Bus Fault BGND Instruction BKPT Instruction 3.10.4.1 External BKPT Signal Once enabled, BDM is initiated whenever assertion of BKPT is acknowledged. If BDM is disabled, a breakpoint exception (vector 0x0C) is acknowledged ...
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... Freescale Semiconductor, Inc. The CPU writes a unique value indicating the source of BDM transition into temporary register A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP and determine the source (refer to mand (RSREG). ATEMP is used in most debugger commands for temporary storage. ...
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... Freescale Semiconductor, Inc. Table 3-6 Background Mode Command Summary Command Mnemonic Read D/A Register RDREG/RAREG Write D/A Register WDREG/WAREG Read System Register RSREG Write System Register WSREG Read Memory Location READ Write Memory Location WRITE Dump Memory Block DUMP Fill Memory Block ...
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... Freescale Semiconductor, Inc. flow of a program under development. Changing the RPC to an odd value will cause an address error when normal mode prefetching begins. 3.10.7.3 Current Instruction Program Counter (PCC) The PCC holds a pointer to the first word of the last instruction executed prior to tran- sition into background mode ...
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... Freescale Semiconductor, Inc. INSTRUCTION CPU REGISTER BUS RCV DATA LATCH PARALLEL OUT PARALLEL IN SERIAL OUT STATUS EXECUTION UNIT SYNCHRONIZE MICROSEQUENCER Figure 3-10 Debug Serial I/O Block Diagram The serial interface uses a full-duplex synchronous protocol similar to the serial periph- eral interface (SPI) protocol. The development system serves as the master of the serial link since it is responsible for the generation of DSCLK ...
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... Freescale Semiconductor, Inc S/C STATUS CONTROL BIT Figure 3-11 BDM Serial Data Word Table 3-7 CPU Generated Message Encoding Bit 16 Data 0 XXXX 0 FFFF 1 0000 1 0001 1 FFFF Command and data transfers initiated by the development system should clear bit 16. The current implementation ignores this bit; however, Motorola reserves the right to use this bit for future enhancements ...
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... Freescale Semiconductor, Inc. instruction pipeline. Pipeline flushes are also signaled with IFETCH. Monitoring these two signals allows a bus state analyzer to synchronize itself to the instruction stream and monitor its activity. 3.10.12 On-Chip Breakpoint Hardware An external breakpoint input and on-chip breakpoint hardware allow a breakpoint trap on any memory access ...
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... Freescale Semiconductor, Inc. MC68F375 REFERENCE MANUAL For More Information On This Product, CENTRAL PROCESSOR UNIT Rev. 25 June 03 Go to: www.freescale.com MOTOROLA 3-28 ...
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... Freescale Semiconductor, Inc. SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E) 4.1 Overview MC68F375 contains the single chip integration module 2 (SCIM2E). The SCIM2E con- sists of several submodules: • The system configuration block controls MCU configuration and operating mode. • The system clock generates clock signals used by the SCIM2E, other IMB mod- ules, and external devices ...
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... Freescale Semiconductor, Inc. SYSTEM CONFIGURATION CLOCK SYNTHESIZER SYSTEM PROTECTION CHIP SELECTS EXTERNAL BUS INTERFACE FACTORY TEST Figure 4-1 SCIM2E Block Diagram 4.2 System Configuration The MCU can operate as a stand-alone device in single-chip mode or it can operate with the support of external memory and/or peripheral devices in the 16-bit or 8-bit expanded modes ...
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... Freescale Semiconductor, Inc. Table 4-1 SCIMMCR Bit Descriptions Bit(s) Name External clock off. 15 EXOFF 0 = The CLKOUT pin is driven during normal operation The CLKOUT pin is placed in a high-impedance state. Freeze software enable. Enables or disables the software watchdog and periodic interrupt timer during background debug mode when FREEZE is asserted. ...
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... Freescale Semiconductor, Inc. 4.2.2 Module Mapping Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte block. The state of the module mapping (MM) bit in SCIMMCR determines where the control register block is located in the system memory map. When register addresses range from 0x7FF000 to 0x7FFFFF; when register addresses range from 0xFFF000 to 0xFFFFFF ...
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... Freescale Semiconductor, Inc. EXOFF disables the CLKOUT external clock output pin by placing the pin in a high- impedance state. CLKOUT is enabled at power-up unless explicitly disabled by writing a zero to EXOFF. CPUD disables the IPIPE/DSO and IFETCH/DSI instruction tracking pins by placing them in a high-impedance state when the MCU is not in background debug mode (BDM) ...
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... Freescale Semiconductor, Inc. 4.3 System Clock The system clock in the SCIM2E provides timing signals for IMB modules and the external bus interface. MC68F375 MCUs are fully static MCU designs; register and memory contents are not affected by clock rate changes. System hardware and soft- ware support clock rate changes during operation ...
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... Freescale Semiconductor, Inc. has a defined relationship to f reset. 4.3.2 Clock Synthesizer Submodule The MC68F375 contains an improved version of the clock synthesizer subsystem. The new architecture accommodates both slow or fast crystal references, see tem Clock Sources. Range of operation and power consumption were taken into consideration when this new architecture was defined ...
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... Freescale Semiconductor, Inc. The filter for both PLL modes consists of resistor R1 connected in series with capacitor C1. This combination is connected between V C2, is also connected between V The following sections describe the clock sub-module in detail. One rule applies to all modes of operation — the actual VCO core frequency must stay at or below two times the maximum allowable system clock frequency ...
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... Freescale Semiconductor, Inc. Extal Pin Amplifier Input Reference Clock Xtal Pin Feedback Frequency Y[5:0] Bits *4(Y+1) W[0] Bit 2w *2(2 ) System Clock Figure 4-2 Slow Reference Mode Figure 4-2 depicts the architecture of the system clock generation circuitry when in this mode. Table 4-6 gives the range of system clock frequencies which may be gen- erated using a 32 ...
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... Freescale Semiconductor, Inc. VCO core frequency can exceed maximum frequency specification are not supported and are left blank reminder, in the table for frequencies above 25 MHz. Select operating frequencies from the table which do not violate the maximum system clock frequency specification. Table 4-6 CLKOUT Frequency: Slow Reference; 32.768 KHz Reference ...
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... Freescale Semiconductor, Inc. 4.3.4 Fast Reference Mode In fast reference mode, the system clock is generated by the PLL from a reference fre- quency much higher than that used in slow reference mode (e.g., four MHz). At reset, the system clock frequency will be equal to twice the reference frequency. This is accomplished by configuring the W bits to multiply by four, and setting the X bit to divide by two for a net result of multiplying by two ...
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... Freescale Semiconductor, Inc. Extal Pin Amp Input Reference Clock Xtal Pin Feedback Frequency W[2:0] Bits *(W+1) System Clock Figure 4-3 Fast Reference Mode MC68F375 SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E) REFERENCE MANUAL For More Information On This Product, Up Phase Comparator Dn VCO Y[2:0] Bits Bit ...
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... Freescale Semiconductor, Inc. Table 4-7 CLKOUT In Fast Reference Mode with 4.0 MHz Reference Y W=000 W=001 X=0 0=000 2,000,000 4,000,000 1=001 1,000,000 2,000,000 2=010 500,000 1,000,000 3=011 250,000 500,000 4=100 125,000 250,000 5=101 62,500 125,000 6=110 31,250 62,500 7=111 31,250 62,500 Y W=000 ...
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... Freescale Semiconductor, Inc. When the MC68F375 is configured in external clock mode, the VCO will be turned off to save power. Changing the unused W bits will have no effect. Y[2:0] Bits /2 EXTAL (Y<6) Figure 4-4 External Clock Mode 4.3.6 Clock Synthesizer Control Register The synthesizer control register (SYNCR) is readable and writable in supervisor mode. ...
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... Freescale Semiconductor, Inc. SYNCR — Synthesizer Control Register, External Clock Mode MSB Reserved Y RESET 4.3.6.1 Frequency control Bits (X,W,Y) Bits [15:8] of the SYNCR control the multiplication or division factors of the synthe- sizer. X bit [15] controls a one-bit divider which drives the system clock in all modes. ...
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... Freescale Semiconductor, Inc. 4.3.6.5 Synthesizer Lock (SLOCK) This read only status bit gives an indication of when the PLL is locked in at the speci- fied frequency. Synthesizer lock occurs when the filter circuit switches from the wide bandwidth to the narrow bandwidth mode (see Filter). ...
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... Freescale Semiconductor, Inc. The PLL loop filter has two bandwidths which are automatically selected. When the PLL is first enabled, the wide bandwidth mode is used which enables the PLL fre- quency to ramp up quickly. Then when the output frequency is near the desired frequency, the filter is switched to the narrow bandwidth to make the final frequency more stable ...
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... Freescale Semiconductor, Inc. 4.3.7.3 Lock Detect Circuit The clock generator subsystem on the MC68F375 also includes an improved lock detect circuit. This lock detect does not depend on frequency over-shoot as did the original circuit also more precise than the original circuit. Basic operation is based on two counters and a “ ...
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... Freescale Semiconductor, Inc. The LOC detector operates in either PLL or external clock modes. When it is triggered, limp mode is entered, the SLIMP bit is set, and an alternate clock is provided as the system clock until edges are detected on the crystal/external clock input. The alternate clock is the output oscillator which is also used as the time-base for the LOC detector ...
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... Freescale Semiconductor, Inc. In order to reset the ports to their post reset state listed in and the reset signal must be present. The clocks are generated with the SCIM2E volt- age controlled oscillator (VCO). The VCO is biased to operate at approximately eight KHz whenever the crystal oscillator is not detected. This feature causes the VCO to start before the crystal oscillator ...
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... Freescale Semiconductor, Inc. When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of the current interrupt mask into the clock control logic. The SCIM2E brings the MCU out of low power stop mode when one of the following exceptions occur: • RESET • ...
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... Freescale Semiconductor, Inc. SETUP INTERRUPT TO WAKE UP MCU FROM LPSTOP NO USING EXTERNAL CLOCK? YES USE SYSTEM CLOCK AS SCIMCLK IN LPSTOP? YES SET STSCIM = 1 f scimclk IN LPSTOP NO WANT CLKOUT ON IN LPSTOP? YES SET STEXT = 1 SET STEXT = clkout sys clkout eclk sys eclk IN LPSTOP IN LPSTOP ENTER LPSTOP 1 ...
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... Freescale Semiconductor, Inc. variations in the output of the RC oscillator due to processing and/or operating conditions. The loss of clock detector can be disabled by writing a one to the loss of clock oscillator bit (LOSCD). This disables the free-running RC oscillator and prevents f being detected. The reset state of LOSCD is zero which enables the RC oscillator and loss of clock detector ...
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... Freescale Semiconductor, Inc. CLOCK PRESCALER Figure 4-7 System Protection 4.4.1 System Protection Control Register SYPCR — System Protection Control Register 7 6 SWE SWP 1 MODCLK Table 4-9 SYPCR Bit Descriptions Bit(s) Name Software watchdog enable 7 SWE 0 = Software watchdog is disabled Software watchdog is enabled. ...
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... Freescale Semiconductor, Inc. Table 4-9 SYPCR Bit Descriptions (Continued) Bit(s) Name Halt monitor enable 3 HME 0 = Halt monitor is disabled Halt monitor is enabled. Bus monitor external enable 2 BME 0 = Disable bus monitor for external bus cycles Enable bus monitor for external bus cycles. BMT[1:0] — Bus Monitor Timing. This field selects the bus monitor timeout period. Refer to ...
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... Freescale Semiconductor, Inc. the halt monitor (HME) enable bit in SYPCR. Refer to more information. 4.4.5 Spurious Interrupt Monitor During interrupt exception processing, the CPU32 normally acknowledges an interrupt request, arbitrates among various sources of interrupt, recognizes the highest priority source, and then acquires a vector or responds to a request for autovectoring. The spurious interrupt monitor asserts the internal bus error signal (BERR interrupt arbitration occurs during interrupt exception processing ...
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... Freescale Semiconductor, Inc. The following equation calculates the timeout period in slow reference mode: Timeout Period The following equation calculates the timeout period in fast reference mode: Timeout Period = The following equation calculates the timeout period in external clock mode: Timeout Period Table 4-12 shows the divide ratio for each combination of the SWP and SWT[1:0] bits ...
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... Freescale Semiconductor, Inc. EXTAL XTAL CRYSTAL 128 OSCILLATOR CLOCK SELECT AND DISABLE SOFTWARE WATCHDOG TIMER SOFTWARE 15 (2 DIVIDER CHAIN — 4 TAPS) WATCHDOG RESET LPSTOP SWE SWT1 SWT0 Figure 4-8 Periodic Interrupt Timer and Software Watchdog Timer 4.4.6.1 Software Watchdog Service Register SWSR — ...
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... Freescale Semiconductor, Inc. The periodic interrupt timer modulus counter is clocked by one of two signals. When the PLL is enabled used in slow reference mode and f ref reference mode. When the PLL is disabled, f prescaler (PTP) bit in the periodic interrupt timer register (PITR) determines system clock prescaling for the periodic interrupt timer. One of two options, either no prescal- ing, or prescaling by a factor of 512, can be selected ...
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... Freescale Semiconductor, Inc. Because of SCIM2E hardware prioritization, a PIT interrupt is serviced before an exter- nal interrupt request of the same priority. The periodic timer continues to run when the interrupt is disabled. Table 4-14 Periodic Interrupt Priority PIRQL[2:0] The PIV field contains the periodic interrupt vector. The vector is placed on the IMB when an interrupt request is made ...
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... Freescale Semiconductor, Inc. PICR — Periodic Interrupt Control Register MSB RESET Table 4-15 PICR Bit Descriptions Bit(s) Name 15:11 — Reserved Periodic interrupt request level. This field determines the priority of periodic interrupt requests. 10:8 PIRQL A value of 0b000 disables PIT interrupts. Periodic interrupt vector. This field specifies the periodic interrupt vector number supplied by the ...
Page 114
... Freescale Semiconductor, Inc. data size acknowledge (DSACK1 and DSACK0) pins. Multiple bus cycles may be required for dynamically sized transfers. To add flexibility and minimize the necessity for external logic, MCU chip-select logic is synchronized with EBI transfers. Refer to 4.5.1 Bus Control Signals The address bus provides addressing information to external devices. The data bus transfers 8-bit and 16-bit data between the MCU and external devices ...
Page 115
... Freescale Semiconductor, Inc DSACK1 DSACK0 W R/ CS5 CS6 IRQ7 ADDR[17:0] DATA[15: CSBOOT MC68F375 V DD MCU CS7 * CS8 CS9 * THESE CHIP-SELECT LINES ARE CONFIGURED FOR 16-BIT PORT OPERATION IN THIS EXAMPLE. Figure 4-9 MCU Basic System MC68F375 SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E) REFERENCE MANUAL ...
Page 116
... Freescale Semiconductor, Inc. 4.5.1.4 Data Strobe Data strobe (DS timing signal. For a read cycle, the MCU asserts DS to signal an external device to place data on the bus asserted at the same time as AS during a read cycle. For a write cycle, DS signals an external device that data on the bus is valid ...
Page 117
... Freescale Semiconductor, Inc. Table 4-18 Address Space Encoding FC2 4.5.1.8 Data Size Acknowledge Signals During normal bus transfers, external devices can assert the data size acknowledge signals (DSACK[1:0]) to indicate port width to the MCU. During a read cycle, these sig- nals tell the MCU to terminate the bus cycle and to latch data. During a write cycle, the signals indicate that an external device has successfully stored data and that the cycle can terminate ...
Page 118
... Freescale Semiconductor, Inc. 4.5.1.11 Autovector Signal The autovector signal (AVEC) can be used to terminate interrupt acknowledgment cycles for external interrupts only. Assertion of AVEC causes the CPU32 to generate vector numbers to locate an interrupt handler routine. If AVEC is continuously asserted, autovectors are generated for all external interrupt requests. AVEC is ignored during all other bus cycles ...
Page 119
... Freescale Semiconductor, Inc word-length operand are OP0 (most significant) and OP1. The single byte of a byte-length operand is OP0. OPERAND 31 LONG WORD OP0 THREE BYTE WORD BYTE Figure 4-10 Operand Byte Order 4.5.3 Operand Alignment The EBI data multiplexer establishes the necessary connections for different combina- tions of address and data sizes ...
Page 120
... Freescale Semiconductor, Inc. to what states DSACK[1:0] must be driven — either by a chip select or by external cir- cuitry — to terminate the given bus cycle. Table 4-20 Operand Alignment Current Transfer Case Cycle 1 Byte to 8-bit port (even) 2 Byte to 8-bit port (odd) 3 Byte to 16-bit port (even) ...
Page 121
... Freescale Semiconductor, Inc. 4.6.1 Synchronization to CLKOUT External devices connected to the MCU bus can operate at a clock frequency different from the frequencies of the MCU as long as the external devices satisfy the interface signal timing constraints. Although bus cycles are classified as asynchronous, they are interpreted relative to the MCU system clock output (CLKOUT) ...
Page 122
... Freescale Semiconductor, Inc. 4.6.2.1 Read Cycle During a read cycle, the MCU transfers data from an external memory or peripheral device. If the instruction specifies a long-word or word operation, the MCU attempts to read two bytes at once. For a byte operation, the MCU reads one byte. The portion of the data bus from which each byte is read depends on operand size, peripheral address, and peripheral port size ...
Page 123
... Freescale Semiconductor, Inc. MCU ADDRESS DEVICE (S0) 1) SET R/W TO WRITE 2) DRIVE ADDRESS ON ADDR[23:0] 3) DRIVE FUNCTION CODE ON FC[2:0] 4) DRIVE SIZ[1:0] FOR OPERAND SIZE ASSERT AS (S1) PLACE DATA ON DATA[15:0] (S2) ASSERT DS AND WAIT FOR DSACK (S3) OPTIONAL STATE (S4) NO CHANGE TERMINATE OUTPUT TRANSFER (S5) 1) NEGATE DS AND AS ...
Page 124
... Freescale Semiconductor, Inc. Fast termination cycles use internal handshaking signals generated by the chip-select logic. To initiate a transfer, the MCU drives the address bus and the SIZ[1:0] signals. When AS, DS, and R/W are valid, a peripheral device either places data on the bus (read cycle) or latches data from the bus (write cycle). At the appropriate time, chip- select logic asserts the DSACK[1:0] signals ...
Page 125
... Freescale Semiconductor, Inc. FUNCTION CODE 2 0 BREAKPOINT ACKNOWLEDGE 2 0 LOW POWER STOP BROADCAST 2 0 INTERRUPT ACKNOWLEDGE Figure 4-13 CPU Space Address Encoding 4.6.4.1 Breakpoint Acknowledge Cycle Breakpoints stop program execution at a predefined point during system development. Breakpoints can be used alone or in conjunction with background debug mode. On the MC68F375 microcontroller, both hardware and software can initiate breakpoints ...
Page 126
... Freescale Semiconductor, Inc. External breakpoint circuitry must decode the function code and address lines, place an instruction word on the data bus, and assert BERR. The CPU32 then performs hardware breakpoint exception processing: it acquires the number of the hardware breakpoint exception vector, computes the vector address from this number, loads the content of the vector address into the PC, and jumps to the exception handler routine at that address ...
Page 127
... Freescale Semiconductor, Inc. BREAKPOINT OPERATION FLOW CPU32 ACKNOWLEDGE BREAKPOINT IF BREAKPOINT INSTRUCTION EXECUTED: 1) SET R/W TO READ 2) SET FUNCTION CODE TO CPU SPACE 3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16] 4) PLACE BREAKPOINT NUMBER ON ADDR[4:2] 5) CLEAR T-BIT (ADDR1) TO ZERO 6) SET SIZE TO WORD 7) ASSERT AS AND DS IF BKPT PIN ASSERTED: ...
Page 128
... Freescale Semiconductor, Inc. 4.6.4.2 LPSTOP Broadcast Cycle Low power stop mode is initiated by the CPU32. Individual modules can be stopped by setting the STOP bits in each module configuration register. The SCIM2E can turn off system clocks after execution of the LPSTOP instruction. When the CPU32 exe- cutes LPSTOP, a low power stop broadcast cycle is generated ...
Page 129
... Freescale Semiconductor, Inc. or after DSACK (case 4), and HALT remains negated; BERR is negated at the same time or after DSACK. • Retry Termination — HALT and BERR are asserted in lieu of, at the same time as, or before DSACK (case 5) or after DSACK (case 6); BERR is negated at the same time or after DSACK ...
Page 130
... Freescale Semiconductor, Inc. If DSACK or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely. 4.6.5.1 Bus Errors The CPU32 treats bus errors as a type of exception. Bus error exception processing begins when the CPU32 detects assertion of the IMB BERR signal (by the internal bus monitor or an external source) while the HALT signal remains negated ...
Page 131
... Freescale Semiconductor, Inc. stack frame during a return from exception (RTE) instruction. Multiple bus errors within a single instruction that can generate multiple bus cycles cause a single bus error exception after the instruction has been executed. Immediately after assertion of a second BERR, the MCU halts and drives the HALT line low ...
Page 132
... Freescale Semiconductor, Inc. During dynamically-sized 8-bit transfers, external bus activity may not stop at the next cycle boundary. Occurrence of a bus error while HALT is asserted causes the CPU32 to initiate a retry sequence. When the MCU completes a bus cycle while the HALT signal is asserted, the data bus goes into a high-impedance state and the AS and DS signals are driven to their inac- tive states ...
Page 133
... Freescale Semiconductor, Inc. indicating that no other bus master is active. This technique allows the processing of bus requests during data transfer cycles negated a few clock cycles after BGACK transition. However, if bus requests are still pending after BG is negated, the MCU asserts BG again within a few clock cycles. ...
Page 134
... Freescale Semiconductor, Inc. When show cycles are enabled asserted externally during internal cycles, and internal data is driven out on the external data bus. Because internal cycles normally continue to run when the external bus is granted, one SHEN[1:0] encoding halts inter- nal bus activity while there is an external master. ...
Page 135
... Freescale Semiconductor, Inc. 4.7.1.1 SCIM2E Reset Control Flow The reset control flow for SCIM2 is depicted in original flow with one exception: After the external system is given the 10 clocks to pull reset high, the reset pin is sampled not high, the external system is given one more opportunity to pull it high ...
Page 136
... Freescale Semiconductor, Inc. Power-on reset (while asserting ext. reset) No PLL locked? Yes 512 clock countdown (while asserting ext. reset) Latch databus config and reconfigure (while asserting ext. reset) 10 clock countdown (external reset is not driven) Ext reset asserted? No Yes 180 clock countdown ...
Page 137
... Freescale Semiconductor, Inc. 4.7.2 Reset Exception Processing The CPU32 processes resets as a type of asynchronous exception. An exception is an event that preempts normal processing and can be caused by internal or external events. Exception processing makes the transition from normal instruction execution to execution of a routine that deals with an exception. Each exception has an assigned vector that points to an associated handler routine ...
Page 138
... Freescale Semiconductor, Inc. Internal byte and aligned word write cycles are guaranteed valid for synchronous resets. External writes will also complete uncorrupted, provided the data bus is condi- tioned with a circuit that incorporates RESET, such as that shown in 4.7.4 Reset Status Register The reset status register (RSR) contains a bit for each reset source in the MCU. When a reset occurs, a bit corresponding to the reset type is set ...
Page 139
... Freescale Semiconductor, Inc. After the 512-clock cycle assertion of the RESET pin, the processing flow for both internal and external resets is the same. The SCIM2E reset control logic will release the RESET pin and read configuration information from BERR, BKPT, and DATA[15:0]. Refer to 4 ...
Page 140
... Freescale Semiconductor, Inc. cycles take. Worst case occurs in slow reference mode and is approximately 15 milli- seconds. During this period, MCU pins may indeterminate state. While pull- up resistors may be used on input only pins, active logic will be required to condition input/output or output only pins. Figure 4-18 depicts the timing of the power-on reset sequence ...
Page 141
... Freescale Semiconductor, Inc. RESET is released. Mode select inputs are driven to the appropriate states at this time. Use an active circuit, such as that shown in 4-24 shows the state of SCIM2E pins during reset. Table 4-24 SCIM2E Pin States During Reset Pin(s) ADDR[2:0] ADDR[10:3]/PB[7:0] ADDR[18:11]/PA]7:0] ...
Page 142
... Freescale Semiconductor, Inc. 4.7.8 Operating Configuration Out of Reset When RESET is released, the SCIM2E acquires setup information from several MCU pins. Individually or in groups, these pins control the four basic areas of MCU config- uration outlined in Table 4-25. Table 4-25 Pins Associated with Basic Configuration Options ...
Page 143
... Freescale Semiconductor, Inc. Table 4-26 Mode Configuration During Reset Mode Pin(s) Affected Select Pin A[18:3] D[15:0] BERR — MODCK — BKPT CSBOOT D0 D[7:0] D1 BR/CS0 FC0/CS3/PC0 D2 FC1/PC1 FC2/CS5/PC2 A19/CS6/PC3 D3-D7 A20/CS7/PC4 D4-D7 A21/CS8/PC5 D5-D7 A22/CS9/PC6 D6 D7 A23/CS10/E D7 DSACK0/PE0 DSACK1/PE1 AVEC/PE2 RMC/PE3 D8 DS/PE4 ...
Page 144
... Freescale Semiconductor, Inc. as normal address bus pins in expanded operating modes. Refer to Reduction in Single-Chip Mode information on the address bus disable bit (ABD). The ADDR[23:19] pins have multiple functions as high-order address lines, chip selects, or discrete outputs and are configured differently depending on operating mode selection and data bus conditioning when RESET is released. The following paragraphs contain a summary of pin configuration options for each external bus configuration ...
Page 145
... Freescale Semiconductor, Inc. DATA15 DATA8 DATA7 DATA0 RESET DS R/W Figure 4-19 Preferred Circuit for Data Bus Mode Select Conditioning Alternate methods can be used for driving data bus pins low during reset. shows two of these options. These simpler circuits do not offer the protection from potential mem- ...
Page 146
... Freescale Semiconductor, Inc. DATA PIN 1 k 1N4148 RESET Figure 4-20 Alternate Circuit for Data Bus Mode Select Conditioning In the simpler of these two circuits, a resistor is connected in series with a diode from the data bus pin to the RESET line. A bipolar transistor can be used for the same pur- pose, but an additional current limiting resistor must be connected between the base of the transistor and the RESET pin ...
Page 147
... Freescale Semiconductor, Inc. Because match conditions do not result in chip-select assertion, the 0b10 (8-bit port) and 0b11 (16-bit port) encodings of the pin assignment fields in CSPAR0 and CSPAR1 serve only to drive pins so configured high at all times. Consequently, any chip select may provide autovector termination, even if its pin assignment field in CSPAR0 or CSPAR1 is programmed with the 0b00 (discrete output) or 0b01 (alternate function) encoding ...
Page 148
... Freescale Semiconductor, Inc. Like ADDR[2:0] (which can be disabled by setting the ABD bit in SCIMMCR), the R/W line and instruction tracking pins (IPIPE/DSO and IFETCH/DSI) can be disabled by setting RWD and CPUD bits in SCIMMCR, respectively. 4.7.8.4 Fully (16-bit) Expanded Mode Operation in 16-bit expanded mode is selected when BERR = 1 and DATA1 = 0 at the release of RESET ...
Page 149
... Freescale Semiconductor, Inc. DATA[7:3] select in a contiguous fashion whether ADDR[23:19]/CS[10:6] serve as high-order address lines or chip selects. between these pins. Table 4-28 Reset Pin Function of CS[10:6] Data Bus Pins at Reset DATA7 DATA6 DATA5 DATA[15:12] allow implementation dependent disabling of on-chip ROM and/or flash EEPROM modules ...
Page 150
... Freescale Semiconductor, Inc. Table 4-30 Partially (8-bit) Expanded Mode Reset Configuration Affected Select Pin Pin(s) or Module(s) 1 CSBOOT NA BR/CS0 FC0/CS3/PC0 1 NA FC1/PC1 FC2/CS5/PC2 ADDR23/CS10/ECLK 1 NA ADDR[22:19]/CS[9:6]/PC[6:3] DSACK0/PE0 DSACK1/PE1 AVEC/PE2 RMC/PE3 DATA8 DS/PE4 AS/PE5 SIZ0/PE6 SIZ1/PE7 FASTREF/PF0 DATA9 IRQ[7:1]/PF[7:1] BGACK/CSE ...
Page 151
... Freescale Semiconductor, Inc. Refer to 3.10.2 Background Debug Mode (CPU32RM/AD) for more information on background debug mode. Refer to the Reference Manual (SCIMRM/AD) ISTICS for more information concerning BKPT signal timing. 4.7.8.6 Emulation Mode Selection The SCIM2E contains logic that can be used to replace on-chip ports externally. The SCIM2E also contains special support logic that allows external emulation of internal ROM ...
Page 152
... Freescale Semiconductor, Inc. When TSC assertion takes effect, internal signals are forced to val- ues that can cause inadvertent mode selection. Once the output drivers change state, the MCU must be powered down and restarted before normal operation can resume. 4.8 Interrupts Interrupt recognition and servicing involve complex interaction between the SCIM2E, the CPU32, and a device or module requesting interrupt service ...
Page 153
... Freescale Semiconductor, Inc. IRQ[6:1] are maskable. IRQ7 is non-maskable. The IRQ7 input is transition sensitive to prevent redundant servicing and stack overflow. A non-maskable interrupt is gener- ated each time IRQ7 is asserted and each time the CCR is written while IRQ7 is asserted. A write to the CCR re-arms the IRQ7 detection circuitry; consequently, any write to the CCR while IRQ7 is asserted, even one that sets the IP field to 0b111, will generate a new IRQ7 interrupt ...
Page 154
... Freescale Semiconductor, Inc. Because the EBI manages external interrupt requests, the SCIM2E IARB field value is used for arbitration between internal and external interrupt requests of the same pri- ority. The reset value of IARB for the SCIM2E is 0b1111, and the reset value of IARB for all other modules is 0b0000 ...
Page 155
... Freescale Semiconductor, Inc. 4.8.4 Interrupt Processing Summary A summary of the entire interrupt processing sequence follows. When the sequence begins, a valid interrupt service request has been detected and is pending. 1. The CPU32 finishes higher priority exception processing or reaches an instruc- tion boundary. 2. Processor state is stacked. ...
Page 156
... Freescale Semiconductor, Inc DSACK1 DSACK0 W R/ CS5 CS6 IRQ7 ADDR[17:0] DATA[15: CSBOOT* MC68F375 V DD MCU 10 K CS7* CS8 CS9* 1. THESE CHIP-SELECT LINES ARE CONFIGURED FOR 16-BIT PORT OPERATION IN THIS EXAMPLE. Figure 4-21 Basic MCU System MC68F375 SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E) REFERENCE MANUAL ...
Page 157
... Freescale Semiconductor, Inc. Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobe, or interrupt acknowledge signals. Chip-select logic can also generate DSACK and AVEC signals internally. Each signal can also be synchronized with the ECLK signal available on ADDR23. When a memory access occurs, chip-select logic compares address space type, address, type of access, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in chip-select registers ...
Page 158
... Freescale Semiconductor, Inc. CSPAR0 — Chip-Select Pin Assignment Register 0 MSB CS5PA[1:0] CS4PA[1:0] RESET DATA2 DATA2 NOTES: 1. The default state of this bit is taken from the listed bit of the data bus during reset. This register contains seven 2-bit fields that determine the function of corresponding chip-select pins. Bits [15:14] are not used. These bits always read zero ...
Page 159
... Freescale Semiconductor, Inc. Table 4-32 CSPAR1 Pin Assignments CSPAR1 Field Chip-Select Signal CS10PA[1:0] CS9PA[1:0] CS8PA[1:0] CS7PA[1:0] CS6PA[1:0] The reset state of DATA[7:3] determines whether pins controlled by CSPAR1 are ini- tially configured as high-order address lines or chip-selects. correspondence between DATA[7:3] and the reset configuration of CS[10:6]/ ADDR[23:19] ...
Page 160
... Freescale Semiconductor, Inc. From the release of reset, chip-select pin functions are determined by logic levels on certain data bus pins. The data bus pins have weak internal pull-up devices but can be held low by external logic. This allows a pin’s 16-bit chip-select function (data bus pin(s) held high) or its alternate function (data bus pin(s) held low selected at the release of RESET ...
Page 161
... Freescale Semiconductor, Inc. Table 4-35 Block Size Encoding BLKSZ[2:0] 000 001 010 011 100 101 110 111 The chip-select address compare logic uses only the most significant bits to match an address within a block. For this reason, the value of the base address must be an inte- ger multiple of the block size ...
Page 162
... Freescale Semiconductor, Inc. CSBAR0 — Chip-Select Base Address Registers CSBAR3 CSBAR5 CSBAR6 CSBAR7 CSBAR8 CSBAR9 CSBAR10 MSB ADDR ADDR ADDR ADDR ADDR ADDR RESET Table 4-36 CSBARBT/CSBAR Bit Descriptions Bit(s) Name Chip-select base address. This field sets the starting address of a particular chip select’s address space ...
Page 163
... Freescale Semiconductor, Inc. CSOR0 — Chip-Select Option Registers CSOR3 CSOR5 CSOR6 CSOR7 CSOR8 CSOR9 CSOR10 MSB MOD BYTE[1:0] R/W[1:0] STRB E RESET CSORBT and CSOR[0], [3] and [5:10] contain parameters that support operations from external memory devices. Bit and field definitions for CSORBT and CSOR[0], [3] and [5:10] are the same ...
Page 164
... Freescale Semiconductor, Inc. Table 4-37 CSOR Bit Descriptions (Continued) Bit(s) Name Address space select. Use this option field to select an address space for the chip-select logic. The CPU32 normally operates in supervisor or user space, but interrupt acknowledge cycles must take place in CPU space ...
Page 165
... Freescale Semiconductor, Inc. Table 4-39 Interrupt Priority Level Field Encoding IPL[2:0] 000 001 010 011 100 101 110 111 NOTES: 1. Any level means that chip select is asserted regardless of the level of the interrupt acknowledge cycle. If the chip select is configured to trigger on an interrupt acknowledge cycle (SPACE[1:0] = 0b00) and the AVEC field is set to one, the chip select automatically generates AVEC and completes the interrupt acknowledge cycle ...
Page 166
... Freescale Semiconductor, Inc. the specified chip select will be asserted. This field only affects the response of chip- select logic to IACK cycles and does not affect interrupt recognition by the CPU32. Setting IPL[2:0] to 0b000 when SPACE[1:0] = 0b00 will cause chip-select assertion regardless of the IACK cycle priority, provided other option register conditions are met. ...
Page 167
... Freescale Semiconductor, Inc. FUNCTION CODE 2 0 INTERRUPT ACKNOWLEDGE Figure 4-23 CPU Space Encoding for Interrupt Acknowledge Chip-select address match logic functions only after the SCIM2E has won arbitration, and the resulting IACK cycle is transferred to the external bus. For this reason, inter- rupt requests from modules other than the SCIM2E will never have their IACK cycles terminated by chip-select generated AVEC or DSACK ...
Page 168
... Freescale Semiconductor, Inc. Table 4-40 Chip-Select Base and Option Register Fields Base address Block size Async/sync Mode Upper/lower byte Read/write AS/DS DSACK Address space Autovector Following reset, the MCU fetches initialization values from the reset vector, beginning at 0x000000 in supervisor program space. The CSBOOT chip-select signal is enabled and can select an external boot device mapped to a base address of 0x000000 ...
Page 169
... Freescale Semiconductor, Inc. Table 4-41 CSBOOT Base and Option Register Fields Base address Block size Async/sync mode Upper/lower byte Read/write AS/DS DSACK Address space Autovector 4.10 General-Purpose Input/Output The SCIM2E has six general-purpose input/output ports and H. (Port C, an output-only port, is included under the discussion of chip-selects). Ports A, B, and G are available in single-chip mode only and port H is available in single-chip and 8- bit expanded modes only ...
Page 170
... Freescale Semiconductor, Inc. If emulation mode is enabled, accesses to the port and H data and data direction registers and the port E pin assignment register are mapped externally, and cause the CSE port emulation chip select to be asserted. The SCIM2E does not respond to these accesses, but allows external logic, such as the Motorola MC68HC33 port replacement unit (PRU), to respond ...
Page 171
... Freescale Semiconductor, Inc. 4.10.3.1 Port E Data Register PORTE0 — Port E0 Data Register PORTE1 — Port E1 Data Register MSB PE7 PE6 PE5 RESET This register can be accessed in two locations and can be read or written at any time. A write to this register is stored in an internal data latch, and if any pin in the corre- sponding port is configured as an output, the value stored for that bit is driven out on the pin ...
Page 172
... Freescale Semiconductor, Inc. [15:8] are reserved and will always read zero. assignments. Table 4-43 Port E Pin Assignments PEPAR Bit PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0 4.10.4 Port F Port F consists of eight I/O pins, a data register, a data direction register, a pin assign- ment register, an edge-detect flag register, an edge-detect interrupt vector register, an edge-detect interrupt level register, and associated control logic ...
Page 173
... Freescale Semiconductor, Inc. IRQ7/PF7 7 IRQ6/PF6 IRQ5/PF5 8 IRQ4/PF4 IRQ3/PF3 IRQ2/PF2 IRQ1/PF1 FASTREF/PF0 PFPAR Figure 4-24 Port F Block Diagram 4.10.4.1 Port F Data Register PORTF0 — Port F Data Register 0 PORTF1 — Port F Data Register 1 MSB PF7 PF6 PF5 RESET This register can be accessed in two locations and can be read or written at any time. ...
Page 174
... Freescale Semiconductor, Inc. 4.10.4.2 Port F Data Direction Register DDRF — Port F Data Direction Register MSB DDF7 DDF6 DDF5 RESET This register controls the direction of the port F pin drivers when pins are configured for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit configures the corresponding pin as an input ...
Page 175
... Freescale Semiconductor, Inc. 4.10.4.4 Port F Edge-Detect Flag Register PORTFE — Port F Edge-Detect Flag Register MSB PEF7 PEF6 PEF5 RESET When the corresponding pin is configured for edge detection, a PORTFE bit is set if an edge is detected. PORTFE bits remain set, regardless of the subsequent state of the corresponding pin, until cleared ...
Page 176
... Freescale Semiconductor, Inc. The SCIM2E will respond to port G data register (PORTG) accesses at any time the MCU is not in emulation mode. Reset has no effect on this register. 4.10.5.1 Port G and H Data Registers PORTG — Port G Data Register PORTH — Port H Data Register MSB 14 13 ...
Page 177
... Freescale Semiconductor, Inc. QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 The MC68F375 includes one independent queued analog-to-digital converter (QADC64) module. For details of QADC64 operation not included in this section, refer to the QADC Reference Manual 5.1 Overview The QADC64 modules consist of an analog front-end and a digital control subsystem, which includes an intermodule bus (IMB3) interface block ...
Page 178
... Freescale Semiconductor, Inc. 5.2 Features The QADC64 module offers the following features: • Internal sample and hold • analog input channels using internal multiplexing • Directly supports up to four external multiplexers (for example, the MC14051) • total input channels with internal and external multiplexing • ...
Page 179
... Freescale Semiconductor, Inc. ANX0 ANX2 ANX4 ANX6 ANX8 ANX10 ANX12 ANX14 ANX1 ANX3 ANX5 ANX7 ANX9 ANX11 ANX13 ANX15 V SSA V DDA SSE AQPDAT[10:8] AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 AN48/PQB4 AN49/PQB5 AN50/PQB6 AN51/PQB7 AN52/MA0/PQA0 AN53/MA1/PQA1 AN54/MA2/PQA2 AN55/ETRIG1/PQA3 AN56/ETRIG2/PQA4 AN57/PQA5 AN58/PQA6 AN59/PQA7 PADS * Not bonded out on this chip. ...
Page 180
... Freescale Semiconductor, Inc. 5.3.1 Port A Pin Functions The eight port A pins can be used as analog inputs bidirectional 8-bit digital input/output port. 5.3.1.1 Port A Analog Input Pins When used as analog inputs, the eight port A pins are referred to as AN[59:52]. Due to the digital output drivers associated with port A, the analog characteristics of port A are different from those of port B ...
Page 181
... Freescale Semiconductor, Inc. 5.3.3 External Trigger Input Pins The QADC64 has two external trigger pins (ETRIG[2:1]). Each of the two external trig- ger pins is associated with one of the scan queues. When a queue is in external trigger mode, the corresponding external trigger pin is configured as a digital input. ...
Page 182
... Freescale Semiconductor, Inc. filtering, which increases reference voltage precision and stability, and subsequently contributes to a higher degree of conversion accuracy. 5.3.7 Dedicated Analog Supply Pins V and V pins supply power to the analog subsystems of the QADC64 module. DDA SSA Dedicated power is required to isolate the sensitive analog circuitry from the normal levels of noise present on the digital power supply ...
Page 183
... Freescale Semiconductor, Inc. power stop mode, the QADC64 requires some recovery time (t APPENDIX E ELECTRICAL after the STOP bit is cleared. In low-power stop mode, the BIU state machine and logic do not shut down: the QADC64MCR and the interrupt register (QADC64INT) are fully accessible and are not reset ...
Page 184
... Freescale Semiconductor, Inc. when the CPU is operating in supervisor mode. Assignable data space can have either restricted to supervisor-only data space access or unrestricted supervisor and user data space accesses. The SUPV bit in QADC64MCR designates the assignable space as supervisor or unrestricted. Attempts to read or write supervisor-only data space when the CPU is not in supervisor mode cause the bus master to assert the internal transfer error acknowledge (TEA) signal ...
Page 185
... Freescale Semiconductor, Inc. Port B pins are referred to as PQB when used as an 8-bit input-only digital port. Port B can also be used for non-multiplexed AN[51:48]/AN[3:0] and multiplexed ANz, ANy, ANx, ANw analog inputs. PORTQA and PORTQB are unaffected by reset. Refer to ister for register and bit descriptions. ...
Page 186
... Freescale Semiconductor, Inc. matically selected from the channel field of the conversion command word (CCW) table, the same as internally multiplexed channels. All of the automatic queue features are available for externally and internally multi- plexed channels. The software selects externally multiplexed mode by setting the MUX bit in QACR0 ...
Page 187
... Freescale Semiconductor, Inc. conversion queues as directly connected signals. Software simply puts the channel number of an externally multiplexed channel into a CCW. Figure 5-3 shows that MA[2:0] may also be analog or digital input pins. When external multiplexing is selected, none of the MA[2:0] pins can be used for analog or digital inputs ...
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... Freescale Semiconductor, Inc. PQA7 CHAN. DECODE & MUX 10-BIT A/D CONVERTER PQA0 PQB7 PQB0 VRH 10 BIT RC D-C VRL VDDA ANALOG POWER COMPAR- ATOR VSSA Figure 5-4 QADC64 Module Block Diagram 5.9.1 Conversion Cycle Times Total conversion time is made up of initial sample time, final sample time, and resolu- tion time ...
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... Freescale Semiconductor, Inc. BUFFER FINAL SAMPLE TIME SAMPLE N CYCLES: TIME 2 CYCLES ( 16) QCLK SAMPLE TIME Figure 5-5 Conversion Timing 5.9.1.1 Amplifier Bypass Mode Conversion Timing If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass (BYP) bit in the CCW, the timing changes to that shown in sample time is eliminated, reducing the potential conversion time by two QCLKs ...
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... Freescale Semiconductor, Inc. 5.9.2 Front-End Analog Multiplexer The internal multiplexer selects one of the 16 analog input pins or one of three special internal reference channels for conversion. The following are the three special channels: • V — Reference voltage high RH • V — Reference voltage low RL • ...
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... Freescale Semiconductor, Inc. table. A queue is a scan sequence of one or more input channels. By using a pause mechanism, subqueues can be created within the two queues. Each queue can be operated using several different scan modes. The scan modes for queue 1 and queue 2 are programmed in QACR1 and QACR2. Once a queue has been started by a trigger ...
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... Freescale Semiconductor, Inc. CONVERSION COMMAND WORD (CCW) TABLE BEGIN QUEUE PAUSE PAUSE END-OF-QUEUE 1 0 BQ2 0 BEGIN QUEUE 2 1 PAUSE 0 1 PAUSE 0 1 PAUSE PAUSE END-OF-QUEUE Figure 5-7 QADC64 Queue Operation with Pause The queue operating mode selected for queue 1 determines what type of trigger event causes the execution of each of the subqueues within queue 1 ...
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... Freescale Semiconductor, Inc. When the QADC64 encounters a CCW with the pause bit set, the queue enters the paused state after completing the conversion specified in the CCW with the pause bit. The pause flag is set and a pause software interrupt may optionally be issued. The sta- tus of the queue is shown to be paused, indicating completion of a subqueue ...
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... Freescale Semiconductor, Inc. Another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue condition occur in the same CCW. Both the pause and end-of-queue conditions are recognized simultaneously. The end-of-queue condition has prece- dence so a conversion is not performed for the CCW and the pause flag is not set. The QADC64 sets the completion flag and the queue status becomes idle ...
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... Freescale Semiconductor, Inc. • Software initiated single-scan mode • External trigger single-scan mode • External gated single-scan mode (queue 1 only) • Interval timer single-scan mode Queue 2 can not be programmed for external gated single-scan mode. In all single-scan queue operating modes, the software must also enable the queue to begin execution by writing the single-scan enable bit to a one in the queue’ ...
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... Freescale Semiconductor, Inc. The QADC64 automatically performs the conversions in the queue until an end-of- queue condition is encountered. The queue remains idle until the software again sets the single-scan enable bit. While the time to internally generate and act on a trigger event is very short, software can momentarily read the status conditions, indicating that the queue is paused ...
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... Freescale Semiconductor, Inc. single-scan enable bit. Software may set the single-scan enable bit again to allow another scan of queue initiated during the next open gate. If the gate closes before queue 1 completes execution, the current CCW completes, execution of queue 1 stops, the single-scan enable bit is cleared, and the PF1 bit is set ...
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... Freescale Semiconductor, Inc. selected. By programming the MQ1(2) field in QACR1(2), the following software initi- ated modes can be selected: • Software initiated continuous-scan mode • External trigger continuous-scan mode • External gated continuous-scan mode (queue 1 only) • Interval timer continuous-scan mode When a queue is programmed for a continuous-scan mode, the single-scan enable bit in the queue control register does not have any meaning or effect ...
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... Freescale Semiconductor, Inc. The software initiated continuous-scan mode keeps the result registers updated more frequently than any of the other queue operating modes. The software can always read the result table to get the latest converted value for each channel. The channels scanned are kept up to date by the QADC64 without software involvement. Software can read a result value at any time ...
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... Freescale Semiconductor, Inc. The purpose of external gated continuous-scan mode is to continuously collect digi- tized samples while the gate is open and to have the most recent samples available. To ensure consistent sample times in waveform digitizing, for example, the program- mer must ensure that all CCW’s have identical sample time settings in IST. ...