MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 425

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

12.6.6 Stop Operation
12.6.7 FREEZE Operation
MC68F375
REFERENCE MANUAL
cycle at the proper time, based on the number of WAIT states programmed into the
WAIT field in the ROMMCR register. The ROM will not drive the IMB3 data bus, since
the data for the cycle will come from the external data pins of the device.
If the Stop bit is asserted, the ROM module will not respond with IAACKB to any
attempts to access the array or the bootstrap information in bootstrap mode. Only the
control register block may be accessed at its normal address. The ROM module must
be in STOP mode in order to allow the EMUL control bit to be changed via an IMB3
write. The ROM module must be in STOP mode and LOCK = 0 in order to allow the
ROMBAH and ROMBAL registers, and the ASPC field of ROMMCR to be written.
STOP also disables bootstrap mode if it set during master reset.
Although the ROMMCR register does not contain a FREEZE mode control bit,
FREEZE mode will affect ROM emulation mode operation. The ROM module monitors
the IFREEZE line on the IMB3 when the ROM is in emulation mode. If IFREEZE is in
its asserted state when the ROM is in emulation mode, the ROM module will respond
to write accesses to the array as well as read accesses, see
Operation
Byte
Aligned Word
Misaligned Word
Aligned Long Word
Misaligned Long Word
NOTES:
1. Access time is shown for 2 clock access, (WAIT[1:0] = 11). An additional clock must be added for
each additional WAIT state programmed in WAIT.
Type of Access
Table 12-6 Minimum ROM Module Access Times
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Bus Cycles for Read
MASK ROM MODULE
Rev. 25 June 03
1
1
2
2
3
1
Number of System Clocks
12.6.5 Emulation Mode
2
2
4
4
6
MOTOROLA
12-11