ST62E60BF1 SGS-Thomson-Microelectronics, ST62E60BF1 Datasheet
ST62E60BF1
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ST62E60BF1 Summary of contents
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R 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125 C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table ...
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ST62T53B/T60B/T63B / ST62E60B . . . . . . . . . . . . . . . . . . . . . .1 1 GENERAL DESCRIPTION . . . . . . . . . . . . ...
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ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST6253B/60B/63B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 1 GENERAL DESCRIPTION . ...
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GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62T53B, ST62T60B, ST62T63B and ST62E60B devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity ap- plications. All ST62xx devices are based on ...
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ST62T53B/T60B/T63B ST62E60B 1.2 PIN DESCRIPTIONS V and V . Power is supplied to the MCU via DD SS these two pins the power connection and the ground connection. SS OSCin and OSCout. These pins are ...
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MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Figure 3. Memory Addressing Diagram PROGRAM SPACE 0000h ...
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ST62T53B/T60B/T63B ST62E60B MEMORY MAP (Cont’d) 1.3.2 Program Space Program Space comprises the instructions to be executed, the data required for immediate ad- dressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the ...
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MEMORY MAP (Cont’d) 1.3.3 Data Space Data Space accommodates all the data necessary for processing the user program. This space com- prises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and ...
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ST62T53B/T60B/T63B ST62E60B MEMORY MAP (Cont’d) 1.3.5 Data Window Register (DWR) The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes locat- ed anywhere in program memory, ...
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MEMORY MAP (Cont’d) 1.3.6 Data RAM/EEPROM Bank (DRBR) Address: E8h — Write only 7 DRBR - - - - - 4 Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page ...
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ST62T53B/T60B/T63B ST62E60B MEMORY MAP (Cont’d) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged as ...
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MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in write mode, ...
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ST62T53B/T60B/T63B ST62E60B 1.4 PROGRAMMING MODES 1.4.1 Option Byte The Option Byte allows configuration capability to the MCUs. Option byte’s content is automatically read, and the selected options enabled, when the chip reset is activated. It can only be accessed during ...
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PROGRAMMING MODES (Cont’d) 1.4.4 EPROM Erasing The EPROM of the windowed package of the MCUs may be erased by exposure to Ultra Violet light. The erasure characteristic of the MCUs is such that erasure begins when the memory is ex- ...
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ST62T53B/T60B/T63B ST62E60B 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and ...
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CPU REGISTERS (Cont’d) However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register. The PC value is incremented after reading the ad- dress of ...
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ST62T53B/T60B/T63B ST62E60B 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ...
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CLOCK SYSTEM (Cont’d) Oscillator Control Registers Address: DCh — Write only 7 OSCR OSCR - - - - 3 2 Bit 7-4. These bits are not used. Bit 3. Reserved. Cleared at Reset. THIS BIT MUST BE SET TO 1 ...
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ST62T53B/T60B/T63B ST62E60B 3.2 RESETS The MCU can be reset in three ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may ...
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RESETS (Cont’d) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. ...
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ST62T53B/T60B/T63B ST62E60B RESETS (Cont’d) Table 7. Register Reset Status Register Oscillator Control Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control AR TIMER Mode Control Register AR TIMER Status/Control 1 Register ...
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DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset ...
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ST62T53B/T60B/T63B ST62E60B DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register (DWDR) . This register is set to ...
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DIGITAL WATCHDOG (Cont’d) 3.3.1 Digital Watchdog Register (DWDR) Address: 0D8h — Read/Write Reset status: 1111 1110b Bit Watchdog Control bit If the hardware option is selected, this bit is forced ...
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ST62T53B/T60B/T63B ST62E60B DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of ...
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INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is asso- ciated with a specific Interrupt Vector which con- tains a Jump instruction to the associated ...
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ST62T53B/T60B/T63B ST62E60B IINTERRUPTS (Cont’d) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know ...
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IINTERRUPTS (Cont’d) 3.4.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed ...
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ST62T53B/T60B/T63B ST62E60B INTERRUPTS (Cont’d) Figure 18. Interrupt Block Diagram FROM REGISTER PORT A,B,C SINGLE BIT ENABLE PBE V DD PORT A PBE PORT B Bits PORT C PBE Bits SPIDIV Register SPINT bit SPIE bit SPIMOD Register OVIE AR TIMER ...
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POWER SAVING MODES The WAIT and STOP modes have been imple- mented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in the following ...
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ST62T53B/T60B/T63B ST62E60B POWER SAVING MODE (Cont’d) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be noted that the ...
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ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: – Input without pull-up or interrupt – Input with pull-up and interrupt – Input with ...
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ST62T53B/T60B/T63B ST62E60B I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option reg- isters ...
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I/O PORTS (Cont’d) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recom- mended safe transitions are illustrated ...
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ST62T53B/T60B/T63B ST62E60B I/O PORTS (Cont’d) Table 13. I/O Port Option Selections MODE AVAILABLE ON PA0-PA3 Input PB0-PB3, PB6-PB7 PC2-PC4 PA0-PA3 Input PB0-PB3, PB6-PB7 with pull up PC2-PC4 Input PA0-PA3 with pull up PB0-PB3, PB6-PB7 PC2-PC4 with interrupt PA0-PA3 Analog Input ...
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I/O PORTS (Cont’d) Figure 21. Peripheral Interface Configuration of SPI, Timer 1 and AR Timer V DD PC3/Sout PC2/Sin PC4/SCK PC1/TIM1 ARTIMin ARTIMout ST62T53B/T60B/T63B ST62E60B PP/OD OUT 1 MUX MISC. REGISTER CLOCK IN CLOCK ...
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ST62T53B/T60B/T63B ST62E60B 4.2 TIMER The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 Figure 22 shows the Timer Block Diagram. The content of the 8-bit ...
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TIMER (Cont’d) 4.2.1 Timer Operation The Timer prescaler is clocked by the prescaler clock input (f 12). INT The user can select the desired prescaler division ratio through the PS2, PS1, PS0 bits. When the TCR count reaches 0, it ...
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ST62T53B/T60B/T63B ST62E60B TIMER (Cont’d) A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i. write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the ...
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AUTO-RELOAD TIMER The Auto-Reload Timer (AR Timer) on-chip pe- ripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as f INT ...
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ST62T53B/T60B/T63B ST62E60B AUTO-RELOAD TIMER (Cont’d) Figure 24 Timer Block Diagram f INT M f 7-Bit /3 INT U AR PRESCALER X PS0-PS2 CC0-CC1 PB6/ ARTIMin SL0-SL1 EF SYNCHRO 42/75 42 DATA BUS 8 DRB7 AR COMPARE REGISTER 8 ...
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AUTO-RELOAD TIMER (Cont’d) It should be noted that the reload values will also affect the value and the resolution of the duty cycle of PWM output signal. To obtain a signal on ARTI- Mout, the contents of the ARCP register ...
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ST62T53B/T60B/T63B ST62E60B AUTO-RELOAD TIMER (Cont’d) Capture Mode with PWM Generation . In this mode, the AR counter operates as a free running 8-bit counter fed by the prescaler output. The counter is incremented on every clock rising edge. An 8-bit ...
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AUTO-RELOAD TIMER (Cont’d) 4.3.3 AR Timer Registers AR Mode Control Register (ARMC) Address: D5h — Read/Write Reset status: 00h 7 TCLD TEN PWMOE EIE CPIE OVIE ARMC1 ARMC0 The AR Mode Control Register ARMC is used to program the different ...
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ST62T53B/T60B/T63B ST62E60B AUTO-RELOAD TIMER (Cont’d) AR Status Control Register 1(ARSC1) Address: D7h — Read/Write 7 PS2 PS1 PS0 D4 SL1 SL0 Bist 7-5 = PS2-PS0: Prescaler Division Selection Bits 2-0. These bits determine the Prescaler divi- sion ratio. The prescaler ...
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A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device depend- ent), offering 8-bit resolution with a typical conver- sion time of ...
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ST62T53B/T60B/T63B ST62E60B A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. Such switching will affect the ...
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SERIAL PERIPHERAL INTERFACE (SPI) The SPI peripheral is an optimized synchronous serial interface with programmable transmission modes and master/slave capabilities supporting a wide range of industry standard SPI specifications. The SPI interface may also implement asynchro- nous data transfer, ...
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ST62T53B/T60B/T63B ST62E60B SERIAL PERIPHERAL INTERFACE SPI(Cont’d) 4.5.1 SPI Registers SPI Mode Control Register (MOD) Address: E2h — Read/Write Reset status: 00h 7 SPRUN SPIE CPHA SPCLK SPIN SPSTRT The MOD register defines and controls the trans- mission modes and characteristics. ...
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SERIAL PERIPHERAL INTERFACE SPI(Cont’d) SPI DIV Register (DIV) Address: E1h — Read/Write Reset status: 00h 7 SPINT DOV6 DIV5 DIV4 DIV3 CD2 The SPIDIV register defines the transmission rate and frame format and contains the interrupt flag. Bits CD0-CD2, DIV3-DIV6 ...
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ST62T53B/T60B/T63B ST62E60B SERIAL PERIPHERAL INTERFACE SPI(Cont’d) 4.6 SPI Timing Diagrams Figure 28. CPOL = 0 Clock Polarity Normal, CPHA = 0 Phase Selection Normal SPRUN SCK Sin Sampling Sout b7 b6 Figure 29. CPOL = 1 Clock Polarity Inverted, CPHA ...
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SERIAL PERIPHERAL INTERFACE SPI(Cont’d) Figure 30. CPOL = 0 Clock Polarity Normal, CPHA = 1 Phase Selection Shifted SPRUN SCK Sin Sampling Sout b7 Figure 31. CPOL = 1 Clock Polarity Inverted, CPHA = 1 Phase Selection Shifted SPRUN SCK ...
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ST62T53B/T60B/T63B ST62E60B 5 SOFTWARE 5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ...
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INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, ...
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ST62T53B/T60B/T63B ST62E60B INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instruc- tions one operand is always the accumulator while the other can be either a ...
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INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. One group either sets or ...
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ST62T53B/T60B/T63B ST62E60B Opcode Map Summary.The following table contains an opcode map for the instructions used by the ST6 LOW 0 1 0000 0001 0010 HI 2 JRNZ 4 CALL abc 0000 1 pcr 2 ext 1 2 ...
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Opcode Map Summary(Continued) LOW 8 9 1000 1001 1010 HI 2 JRNZ abc 0000 1 pcr 2 ext 1 2 JRNZ abc 0001 1 pcr 2 ext 1 2 JRNZ ...
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ST62T53B/T60B/T63B ST62E60B 6 ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher ...
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RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A V Operating Supply Voltage Oscillator Frequency OSC I Pin Injection Current (positive) INJ+ I Pin Injection Current (negative) V INJ- Notes: 1. Care must be taken in ...
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ST62T53B/T60B/T63B ST62E60B 6.3 DC ELECTRICAL CHARACTERISTICS (T = -40 to +125 C unless otherwise specified) A Symbol Parameter V Input Low Level Voltage IL All Input pins V Input High Level Voltage IH All Input pins (1) Hysteresis Voltage V ...
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AC ELECTRICAL CHARACTERISTICS (T = -40 to +125 C unless otherwise specified) A Symbol Parameter (1) t Supply Recovery Time REC Minimum Pulse Width (V T RESET pin WR NMI pin T EEPROM Write Time WEE (2) Endurance EEPROM ...
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ST62T53B/T60B/T63B ST62E60B 6.6 TIMER CHARACTERISTICS (T = -40 to +125 C unless otherwise specified) A Symbol Parameter f Input Frequency on TIMER Pin IN t Pulse Width at TIMER Pin W 6.7 SPI CHARACTERISTICS (T = -40 to +125 C ...
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GENERAL INFORMATION 7.1 PACKAGE MECHANICAL DATA Figure 33. 20-Pin Plastic Dual In-Line Package, 300-mil Width Figure 34. .20-Pin Plastic Small Outline Package, 300-mil Width ST62T53B/T60B/T63B ST62E60B Dim. A ...
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... Figure 35. 20-Pin Ceramic Dual In Line Package, 300-mil Width 7.2 ORDERING INFORMATION Table 25. OTP/EPROM VERSION ORDERING INFORMATION Program Sales Type Memory (Bytes) ST62T53BB6 ST62T53BB3 1836 (OTP) ST62T53BM6 ST62T53BM3 ST62T60BB6 ST62T60BB3 3884 (OTP) ST62T60BM6 ST62T60BM3 ST62T63BB6 1836 (OTP) ST62T63BM6 ST62E60BF1 3884 (EPROM) 66/ Dim. Min Typ Max A 2.35 A1 0.10 B 0.33 C 0.23 D 12.60 D1 ...
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R 8-BIT FASTROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125 C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table ...
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ST62P53B/P60B/P63B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62P53B, ST62P60B and ST62P63B are the F actory A dvanced S ervice T echnique ROM (FASTROM) versions of ST62T53B, ST6260B and ST62T63B OTP devices. They offer the same functionality as OTP devices, selecting ...
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ST62P53B, ST62P60B and ST62P63B FASTROMMICROCONTROLLER OPTION LIST Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address . . ...
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ST62P53B/P60B/P63B Notes: 70/75 70 ...
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R 8-BIT ROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125 C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table ...
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ST6253B/60B/63B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6253B, ST6260B and ST6263B are mask programmed ROM versions of ST6260B and ST62T63B OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable ...
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ST6253B, ST6260B and ST6263BMICROCONTROLLER OPTION LIST Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address . . . ...
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ST6253B/60B/63B 1.3 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to SGS-THOMSON. 1.3.1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected mask options. ...
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Notes: Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from ...