YMF740C-V Yamaha, YMF740C-V Datasheet
YMF740C-V
Specifications of YMF740C-V
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YMF740C-V Summary of contents
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... MPU401 UART mode MIDI interface Joystick • Supports AC’97 Interface (AC-Link) • Hardware Volume Control • Single Crystal operation (24.576MHz) • 5V Power supply for I/O. 3.3V Power supply for Internal core logic • 144-pin LQFP (YMF740C-V) YMF740C CATALOG CATALOG No.:LSI-4MF740C20 September 21, 1998 January 14, 1999 ...
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... YMF740C PIN CONFIGURATION YMF740C-V GP4 1 2 GP5 GP6 3 4 GP7 RXD 5 6 TXD VOLDW VOLUP# VDD5 9 10 VDD3 VSS 11 12 VSS IRQ5 13 14 IRQ7 IRQ9 15 16 IRQ10 IRQ11 17 18 INTA# VSS 19 20 RST# VDD5 21 22 PVSS PCICLK 23 24 PVDD GNT# ...
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... YMF740C PIN DESCRIPTION 1. PCI Bus Interface (52-pin) name I/O PCICLK I RST# I AD[31:0] IO C/BE[3:0]# IO PAR IO FRAME# IO IRDY# IO TRDY# IO STOP# IO IDSEL I DEVSEL# IO REQA# O GNTA# I PCREQ# O PCGNT# I PERR# IO SERR# O INTA Legacy Device Interface (16-pin) name I/O IRQ5 O IRQ7 O IRQ9 O IRQ10 O IRQ11 O GP[3:0] I GP[7:4] I GREF I RXD I TXD O Type ...
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... YMF740C 3. AC’97 Interface (6-pin) name I/O CRST# O CMCLK O CBCLK I CSDO O CSDI I CSYNC O 4. Miscellaneous (14-pin) name I/O VOLUP# I VOLDW# I XI24 I XO24 O TEST[7:4,2:0]# I TEST3# IO LOOPF[1: Power Supply (39-pin) name I/O PVDD[5:0] - PVSS[14:0] - LVDD - LVSS - VDD3[3:0] - VDD5[3:0] - VSS[7:0] - TYPE T : TTL Ttr : Tri-State TTL Tup : Pull up (Max. 300kohm) TTL Note) All pins except the above pins are NC (No Connection) pins ...
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... YMF740C BLOCK DIAGRAM Legacy Audio PC-PCI SB Pro MPU401 Joystick PCI Bus BUS Master Interface DMA Controller Memory Rate Converter FM / Mixer PCI Audio XG Synthesizer Direct Sound Acc. Wave In/Out -5- AC'97 Interface January 14, 1999 ...
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... YMF740C SYSTEM DIAGRAM -6- January 14, 1999 ...
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... YMF740C FUNCTION OVERVIEW 1. PCI INTERFACE DS-1L supports the PCI bus interface and complies to PCI revision 2.1. 1-1. PCI Bus Command DS-1L supports the following PCI Bus commands. 1-1-1. Target Device Mode C/BE[3:0 ...
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... YMF740C 1-2. PCI Configuration Register In addition to the Configuration Register defined by PCI Revision 2.1, DS-1L provides proprietary PCI Configuration Registers in order to control legacy audio function, such as FM Synthesizer, Sound Blaster Pro, MPU401 and Joystick. These additional registers are configured by BIOS or the configuration software from YAMAHA Corporation. ...
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... YMF740C 00 - 01h: Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b[15:0] ........Vendor ID This register contains the YAMAHA Vendor ID registered in Revision 2.1. This register is hardwired to 1073h 03h: Device ID Read Only Default: 000Ch Access Bus Width: 8, 16, 32-bit b15 ...
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... YMF740C b8................SER: SERR# Enable This bit enables DS-1L to drive SERR#. “0”: Do not drive SERR#. “1”: Drives SERR# when DS-1L detects an Address Parity Error on normal target cycle or a Data Parity Error on special cycle 07h: Status Read / Write Clear Default: 0210h Access Bus Width: 8, 16, 32-bit ...
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... YMF740C 08h: Revision ID Read Only Default: 03h Access Bus Width: 8, 16, 32-bit Revision ID b[7:0] ..........Revision ID This register contains the revision number of DS-1L. This register is hardwired to 03h. 09h: Programming Interface Read Only Default: 00h Access Bus Width: 8, 16, 32-bit Programming Interface b[7:0] ...
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... YMF740C 0Dh: Latency Timer Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit Latency Timer b[7:0] ..........Latency Timer When DS-1L becomes a Bus Master device, this register indicates the initial value of the Master Latency Timer. 0Eh: Header Type Read Only Default: 00h ...
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... YMF740C 2C-2Dh: Subsystem Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b[15:0] ........Subsystem Vendor ID This register contains the Subsystem Vendor ID. In general, this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor. This register is read only. To write the IHV’ ...
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... YMF740C 3Ch: Interrupt Line Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit Interrupt Line b[7:0] ..........Interrupt Line This register indicates the interrupt channel that INTA# is assigned to. 3Dh: Interrupt Pin Read Only Default: 01h Access Bus Width: 8, 16, 32-bit b7 b6 ...
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... YMF740C 40 - 41h: Legacy Audio Control Read / Write Default: 907Fh Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 ” 0 ” LAD MPUIRQ b0................SBEN: Sound Blaster Enable This bit enables the mapping of the Sound Blaster Pro block in the I/O space specified by the SBIO bits, when LAD is set to “ ...
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... YMF740C b[7:6] ..........SDMA: Sound Blaster DMA-8 Channel Select These bits select the DMA channel for the Sound Blaster Pro block. “0”: DMA ch0 “1”: DMA ch1 “2”: reserved “3”: DMA ch3 b[10:8] ........SBIRQ: Sound Blaster IRQ Channel Select These bits select the interrupt channel for the Sound Blaster Pro block. ...
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... YMF740C 42 - 43h: Extended Legacy Audio Control Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 IMOD SBVER SMOD b[1:0] ..........FMIO: FM I/O Address allocation These bits determine the base I/O address for the of the FM Synthesizer block (FMBase). FM Synthesizer block uses 4 bytes in the I/O address space. ...
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... YMF740C b[12:11] ......SMOD: SB DMA mode These bits determine the protocol to achieve the DMAC(8237) function on the PCI bus. “0”: PC/PCI “1” - “3”: reserved b[14:13] ......SBVER: SB Version Select These bits set the version of the SB Pro DSP. The value set in these bits is returned by sending the E1h DSP command. “ ...
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... YMF740C 48-49h: DS-1L Control Register Read / Write Default: 0001h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 - - - - b0................CRST: AC’97 Software Reset Signal Control This bit controls the CRST# signal. “0”: Inactive (CRST#=High) “1”: Active (CRST#=Low) 4A-4Bh: DS-1L Power Control Register ...
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... YMF740C b5................PSN: Power Save PCI Audio block Setting this bit to “1” stops providing the clock with the PCI Audio function block. This block includes PCI Audio, SRC, AC’97 I/F and H/W Vol. “0”: Normal (default) “1”: Power Save b8................PR0: AC’97 Power down Control 0 This bit controls the power state of the ADC and Input Mux in AC’ ...
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... YMF740C Master (24.576MHz) DMC PCICLK (33MHz) - Set DPLL0, DPLL1, PSL0, PSL1 and PSN bits to “1”, when DMC bit is set to “1”. - Set PSL0 and PSL1 bits to “1”, when DPLL0 bit is set to “1”. - Set PSN bit to “1”, when DPLL1 bit is set to “1”. ...
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... YMF740C 50h: Capability ID Read Only Default: 01h Access Bus Width: 8, 16, 32-bit Capability ID b[7:0] ..........Capability ID: Capability Identifier This register indicates that the new capability register is for Power Management control. This register is hardwired to 01h. 51h: Next Item Pointer Read Only Default: 00h ...
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... YMF740C 54-55h: Power Management Control / Status Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 - - - - b[1:0] ..........PS: Power State These bits determine the power state of DS-1L. DS-1L supports the following power states: “0”: D0 “1”: D1 (not supported) “2”: D2 “3”: ...
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... YMF740C 2. ISA Compatible Device DS-1L contains the following functions to maintain the compatibility with the past ISA Sound Devices. These devices are considered Legacy devices and the functions are referred to as Legacy Audio. Legacy Audio is independent from PCI Audio and can be used simultaneously. ...
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... YMF740C 2-1. FM Synthesizer Block FM Synthesizer Block is register compatible with YMF289B. However, Power Management register has been deleted because it is now controlled by the PCI Configuration Register. The following shows the FMBase I/O map of FM Synthesizer. FMBase (R) FMBase (W) FMBase+1 (R/W) FMBase+2 (W) FMBase+3 (R/W) The default FMBase value is 0x0388. ...
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... YMF740C 2-1-2. FM Synthesizer Data Register FM Synthesizer Data Register Array 0 (R/W): Address D7 D6 00-01h 02h 03h 04h RST MT1 08h - NTS (*1) 20-35h AM VIB (*2) 40-55h KSL (*3) 60-75h (*4) 80-95h A0-A8h B0-B8h - - BDh DAM DVB C0-C8h *6 *6 (*5) E0-F5h - - FM Synthesizer Data Register Array 1 (R/W) Address D7 D6 00-01h 04h - - 05h ...
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... YMF740C 2-2. Sound Blaster Pro Block This block emulates the DSP commands of Sound Blaster and Sound Blaster Pro. Only playback functions are supported (record functions are not supported). However, to maintain compatibility for games designed so that every DSP command receives a correct response. ...
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... YMF740C 2-2-1. DSP Command The following shows the list of DSP Commands that are supported by the SB Pro engine. Both SB and SB Pro commands are supported. CMD Support Function 10h o 8bit direct mode single byte digitized sound output 14h o 8bit single-cycle DMA mode digitized sound output ...
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... YMF740C 2-2-2. Sound Blaster Pro Mixer The following shows the register map of the Mixer section of Sound Blaster Pro. Address b7 b6 00h 04h Voice Volume L 0Ah - - 0Ch - - 0Eh - - 22h Master Volume L 26h MIDI Volume L 28h CD Volume L* 2Eh Line Volume L* F0h SBPDA - F1h F8h ...
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... YMF740C (1) Volume for MIDI 0 mute 0 0000h mute 1 0000h mute 2 0000h mute 3 0000h mute 4 0000h mute 5 0000h mute 6 0000h mute 7 0000h The default is Master = 4, MIDI = 4 (-12dB). (2) Volume for Voice 0 mute 0 0000h mute 1 0000h mute 2 0000h mute 3 0000h mute 4 0000h mute 5 0000h mute ...
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... YMF740C 2-2-3. SB Suspend / Resume The SB block can read the internal state as to support Suspend and Resume functions. The internal state is made up of 218 flip flops. To read the state, these states are shifted in order and read 8 bits at a time from the SCAN DATA register. ...
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... YMF740C F1h: Scan In/ Out Data Read / Write Default: 00h SCAN DATA b[7:0] ..........SCAN DATA This is the data port for reading and writing the internal state. F8h: Interrupt Flag Register Read Only Default: 00h b0................SBI: SB Interrupt Flag This bit indicates that the SB DSP occurs the interrupt. This bit is read only. Thus, read the SB DSP read port to clearing the interrupt and this bit ...
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... YMF740C 2-3. MPU401 This block is for transmitting and receiving MIDI data compatible with UART mode of “MPU401”. Full duplex operation is possible using the 16-byte FIFO for each direction, transmitting and receiving. The following shows the MPUBase I/O map for MPU401. MPUBase (R/W) MPUBase + 1h ...
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... YMF740C 3. DMA Emulation Protocol The former synthesizer LSI for the ISA bus such as the Sound Blaster used the DMA controller (8237: ISA DMAC) on the system to transfer the sound data from/to the host. For DS-1L, however, ISA DMAC must be used to transfer the sound data to the Sound Blaster Pro Block of the Legacy Audio Block ...
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... YMF740C 4. Interrupt Routing DS-1L supports two types of interrupts, interrupt signal on the PCI bus (INTA#) and interrupt signal on the ISA bus (IRQ[5,7,9,10,11]). The IRQs on DS-1L are routed as shown below. INTA# INTA IRQ5 IRQ7 ISA IRQ IRQ9 IRQ10 IRQ11 PCI Audio can only use INTA#, but the Sound Blaster Pro and MPU401 blocks of the Legacy Audio Block can use any of the two protocols ...
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... YMF740C 5. Hardware Volume Control The hardware volume control determines the AC’97 master volume without using any software control using the external circuit listed below. Two pins, VOLUP# for increasing the volume and VOLDW# for decreasing the volume, are used. DS-1L provides a shadow register for the AC’97 master volume. When the software accesses the AC’97 Master Volume always reflected in the shadow register ...
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... YMF740C ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Item Power Supply Voltage 1 (PVDD, VDD5) Power Supply Voltage 2 (VDD3, LVDD) Input Voltage 1 (PVDD, VDD5) Input Voltage 2 (VDD3, LVDD) Operating Ambient Temperature Storage Temperature Note : PVSS=LVSS=VSS=0[V] 2. Recommended Operating Conditions Item Power Supply Voltage 1 (PVDD, VDD5) ...
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... YMF740C 3. DC Characteristics Item High Level Input Voltage 1 Low Level Input Voltage 1 High Level Input Voltage 2 Low Level Input Voltage 2 High Level Input Voltage 3 Low Level Input Voltage 3 High Level Input Voltage 4 Low Level Input Voltage 4 Input Leakage Current High Level Output Voltage 1 ...
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... YMF740C 4. AC Characteristics 4-1. Master Clock (Fig.1) Item XI24 Cycle Time XI24 High Time XI24 Low Time Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V XI24 4-2. Reset (Fig.2) Item Reset Active Time after Power Stable Power Stable to Reset Rising Edge Reset Slew Rate Note : Top = 0-70° ...
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... YMF740C 4-3. PCI Interface (Fig.3, 4) Item PCICLK Cycle Time PCICLK High Time PCICLK Low Time PCICLK Slew Rate PCICLK to Signal Valid Delay Float to Active Delay Active to Float Delay Input Setup Time to PCICLK Input Hold Time for PCICLK Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0 *10: This characteristic is applicable to REQ# and PCREQ# signal ...
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... YMF740C 4-4. AC’97 Master Clock Item CMCLK Cycle Time CMCLK High Time CMCLK Low Time CMCLK Rising Time CMCLK Falling Time Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0 CMCLK (Fig.5) Symbol Min. Typ 40.69 CMCYC CMHIGH ...
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... YMF740C 4-5. AC-link (Fig.6) Item CBCLK Cycle Time CBCLK High Time CBCLK Low Time CSYNC Cycle Time CSYNC High Time CSYNC Low Time CBCLK to Signal Valid Delay Output Hold Time for CBCLK Input Setup Time to CBCLK Input Hold Time for CBCLK Warm Reset Width Note) Top = 0-70° ...
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... YMF740C EXTERNAL DIMENSIONS YMF740C-V 109 144 LEAD THICKNESS : 0.15+0.10 The shape of the molded corner may slightly different from the shape in this diagram. The figure in the parenthesis ( ) should be used as a reference. Plastic body dimensions do not include burr of resin. UNIT : mm Note : The LSIs for surface mount need especial consideration on storage and soldering conditions. ...
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... YMF740C 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document ...