M24128-WMN6 SGS-Thomson-Microelectronics, M24128-WMN6 Datasheet

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M24128-WMN6

Manufacturer Part Number
M24128-WMN6
Description
256 KBIT/128 KBIT SERIAL I 2 C BUS EEPROM WITHOUT CHIP ENABLE LINES
Manufacturer
SGS-Thomson-Microelectronics
Datasheet

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DESCRIPTION
These I
grammable memory (EEPROM) devices are orga-
nized as 32Kx8 bits (M24256) and 16Kx8 bits
(M24128), and operate down to 2.5 V (for the -W
version of each device).
The M24256 and M24128 are available in Plastic
Dual-in-Line and Plastic Small Outline packages.
These memory devices are compatible with the
I
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
accordance with the I
Table 1. Signal Names
November 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
2
C extended memory standard. This is a two wire
Compatible with I
Two Wire I
Supports 400 kHz Protocol
Single Supply Voltage:
– 4.5V to 5.5V for M24xxx
– 2.5V to 5.5V for M24xxx-W
Hardware Write Control
BYTE and PAGE WRITE (up to 64 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Behavior
100,000 Erase/Write Cycles (minimum)
40 Year Data Retention (minimum)
SDA
SCL
WC
V
V
CC
SS
2
C-compatible electrically erasable pro-
2
C Serial Interface
2
C Extended Addressing
2
Serial Data/Address Input/
Output
Serial Clock
Write Control
Supply Voltage
Ground
C bus definition.
256/128 Kbit Serial I²C Bus EEPROM
Figure 1. Logic Diagram
Without Chip Enable Lines
150 mil width
8
SCL
WC
SO8 (MN)
1
0.25 mm frame
V CC
8
PSDIP8 (BN)
V SS
M24256
M24128
1
PRELIMINARY DATA
8
200 mil width
SO8 (MW)
M24256
M24128
1
SDA
AI01882
1/16

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M24128-WMN6 Summary of contents

Page 1

... C-compatible electrically erasable pro- grammable memory (EEPROM) devices are orga- nized as 32Kx8 bits (M24256) and 16Kx8 bits (M24128), and operate down to 2.5 V (for the -W version of each device). The M24256 and M24128 are available in Plastic Dual-in-Line and Plastic Small Outline packages. ...

Page 2

... M24256, M24128 Figure 2A. DIP Connections M24256 M24128 AI01883 Note Not Connected The memory behaves as a slave device in the I protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master ...

Page 3

... SCL. For correct device operation, the SDA signal must be stable during the clock low-to-high transi- tion, and the data must change only when the SCL line is low. BUS fc = 100kHz fc = 400kHz 100 C BUS (pF) M24256, M24128 2 ) for Bus SDA MASTER ...

Page 4

... M24256, M24128 2 Figure Bus Protocol SCL SDA START CONDITION SCL MSB SDA START CONDITION 1 SCL MSB SDA Memory Addressing To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends the 8-bit byte, shown in Table 3, on the SDA bus line (most significant bit first) ...

Page 5

... the byte in memory. Bit b15 is treated as a Don’t Care bit on the M24256 memory. Bits b15 and b14 are treated as Don’t Care bits on the M24128 memory. ACK ACK BYTE ADDR BYTE ADDR R/W ACK ACK BYTE ADDR ...

Page 6

... M24256 and b13-b6 for the M24128) are the same. If more bytes are sent than ACK ACK DATA IN ...

Page 7

... Device Select Code (the first byte of the new instruction). – Step 2: if the memory is busy with the internal write cycle, no Ack will be returned and the mas- ter goes back to Step 1. If the memory has ter- M24256, M24128 Proceed Random Address READ Operation AI01847 ...

Page 8

... M24256, M24128 Figure 8. Read Mode Sequences CURRENT ADDRESS DEV SEL READ RANDOM ADDRESS DEV SEL * READ SEQUENTIAL CURRENT DEV SEL READ SEQUENTIAL RANDOM DEV SEL * READ ACK Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 ...

Page 9

... 2.1 mA ° 400 kHz) A Test Condition Figure 9. AC Testing Input Output Waveforms 50 ns 0.8V CC 0. 0.2V CC 0. M24256, M24128 Min SDA –0.3 0.3V 0.7V CC –0 Min. Max 500 100 Max ...

Page 10

... In all read modes, the memory waits, after each byte read, for an acknowledgment during the 9 bit time. If the master does not pull the SDA line low during this time, the memory terminates the data transfer and switches to its stand-by state. M24256 / M24128 V =2 Unit T =– ...

Page 11

... SDA IN START CONDITION SCL tCLQV SDA OUT SCL SDA IN tCHDH STOP CONDITION tCHCL tDLCL tCHDX tCLDX SDA SDA INPUT CHANGE tCLQX DATA VALID DATA OUTPUT tW WRITE CYCLE M24256, M24128 tCLCH tDXCX tCHDH tDHDL STOP & BUS FREE tCHDX START CONDITION AI00795B 11/16 ...

Page 12

... V to 5.5 V blank W 2 5.5 V Note: 1. Available only on request. 2. Available for M24128 only. 3. Available for M24256 only. ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all ‘1’s (FFh). The notation used for the device number is as shown in Table 11 ...

Page 13

... M24256, M24128 inches Typ. Min. Max. 0.154 0.232 0.019 0.130 0.209 0.014 0.022 0.045 0.065 0.008 0.014 0.362 0.390 0.300 – 0.236 0.264 0.100 – 0.307 0.394 0.118 0.150 ...

Page 14

... M24256, M24128 Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width Symb. Typ 1. Figure 12. SO8 narrow (MN SO-a Note: 1. Drawing is not to scale. 14/16 mm Min. Max. 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 – – 5.80 6.20 0.25 0.50 0.40 0.90 0° 8° inches Typ. Min. ...

Page 15

... Min. Max. 2.03 0.10 0.25 1.78 0.35 0.45 – – 5.15 5.35 5.20 5.40 – – 7.70 8.10 0.50 0.80 0° 10° M24256, M24128 inches Typ. Min. 0.004 0.014 0.008 – 0.203 0.205 0.050 – 0.303 0.020 0° Max. 0.080 0.010 0.070 0.018 – 0.211 0.213 – 0.319 0.031 10° ...

Page 16

... M24256, M24128 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

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