M36DR432A SGS-Thomson-Microelectronics, M36DR432A Datasheet
M36DR432A
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M36DR432A Summary of contents
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... Fast Program (optional) PPF ACCESS TIME: 100,120ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code, M36DR432A: 00A0h – Bottom Device Code, M36DR432B: 00A1h FLASH MEMORY 32 Mbit (2Mb x16) BOOT BLOCK – Parameter Blocks (Top or Bottom Location) PROGRAMMING TIME – ...
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... M36DR432A, M36DR432B DESCRIPTION The M36DR432 is a multichip memory device con- taining a 32 Mbit boot block Flash memory and a 4 Mbit of SRAM. The device is offered in a Stacked LFBGA66 (0.8 mm pitch) package. The two components are distinguished by use with three chip enable inputs: EF for the Flash memory and, E1S and E2S for the SRAM ...
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... A15 A14 A11 A13 A8 A10 A9 DQ15 NC DQ13 RPF DQ12 V PPF A19 DQ11 UBS GS DQ9 A17 M36DR432A, M36DR432B A12 V SSF DQ14 DQ7 DQ6 DQ4 DQ5 E2S V DDS V DDF DQ10 DQ2 DQ3 DQ8 DQ0 DQ1 A2 A1 E1S ...
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... M36DR432A, M36DR432B Table 2. Absolute Maximum Ratings Symbol T Ambient Operating Temperature A T Temperature Under Bias BIAS T Storage Temperature STG (2) Input or Output Voltage Flash Chip Supply Voltage DDF V SRAM Chip Supply Voltage DDS V Program Voltage PPF Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device ...
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... DDS power supply for all operations (Read, Program). V SSF reference for all voltage measurements respec- tively in the Flash and SRAM chips. M36DR432A, M36DR432B . The memory will recover from PLQ7V PHQ7V2 , the lockable blocks are protected. Pro the lockable blocks are un- ...
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... M36DR432A, M36DR432B Table 3. Main Operation Modes Operation Mode Read Write Block Locking V Standby Reset Output Disable Read Flash must be disabled Write Flash must be disabled Standby/ Power Any Flash mode is allowable ...
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... Data is internally read and stored in a page buffer. The page has a size of 4 words M36DR432A, M36DR432B and is addressed by A0-A1 address inputs. Read operations of the Electronic Signature, the Status Register, the CFI, the Block Protection Status, the ...
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... M36DR432A, M36DR432B Table 4. Bank Size and Sectorization Bank A Bank B Table 5. Bank A, Top Boot Block Addresses M36DR432A Size # Address Range (KWord 1FF000h-1FFFFFh 1 4 1FE000h-1FEFFFh 2 4 1FD000h-1FDFFFh 3 4 1FC000h-1FCFFFh 4 4 1FB000h-1FBFFFh 5 4 1FA000h-1FAFFFh 6 4 1F9000h-1F9FFFh 7 4 1F8000h-1F8FFFh 8 32 1F0000h-1F7FFFh 9 32 1E8000h-1EFFFFh 10 32 ...
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... M36DR432A, M36DR432B 18 32 0D0000h-0D7FFFh 17 32 0C8000h-0CFFFFh 16 32 0C0000h-0C7FFFh 15 32 0B8000h-0BFFFFh 14 32 0B0000h-0B7FFFh 13 32 0A8000h-0AFFFFh 12 32 0A0000h-0A7FFFh 11 32 098000h-09FFFFh 10 32 090000h-097FFFh 9 32 ...
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... M36DR432A, M36DR432B Table 9. User Bus Operations Operation EF Write V V Output Disable V Standby Reset / Power Down X V Block Locking Note Don't care. Table 10. Read Electronic Signature (AS and Read CFI instructions) Code Device Manufacturer Code M36DR432A Device Code M36DR432B Table 11. Read Block Protection (AS and Read CFI instructions) ...
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... A subsequent read will output the Manufacturer or the Device Code (Electronic Sig- nature), the Block Protection status or the Config- uration Register status depending on the levels of A0 and A1 (see Table 10, 11 and 12). A7-A2 must M36DR432A, M36DR432B Command Bypass Reset Bank Erase Confirm Unlock Bypass Block Erase Resume/Confirm ...
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... M36DR432A, M36DR432B The bank address is don’t care for this instruction. The Electronic Signature can be read from the memory allowing programming equipment or ap- plications to automatically match their interface to the characteristics of Flash Chip. The Manufactur- er Code is output when the address lines A0 and ...
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... It will result in DQ6 toggling when the data is being programmed. Erase Resume (ER) Instruction. If Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h address within the bank be- ing erased and without any Coded Cycle. M36DR432A, M36DR432B an Erase 13/46 ...
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... M36DR432A, M36DR432B (1) Table 14. Protection States (2) Program/Erase Current State Allowed (WP, DQ1, DQ0) 100 yes 101 no 110 yes 111 no 000 yes 001 no 011 no Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WPF status. 2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Autoselect instruction with ...
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... Blocks not being erased then Resume Erase. Data B0h Bank Addr. Address Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time Data 30h M36DR432A, M36DR432B 3rd Cyc. 4th Cyc. 5th Cyc. completes. Program Address 2 Note 6, 7 Program ...
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... M36DR432A, M36DR432B STATUS REGISTER BITS P/E.C. status is indicated during execution by Data Polling on DQ7, detection of Toggle on DQ6 and DQ2, or Error on DQ5 bits. Any read attempt within the Bank being modified and during Program or Erase command execution will automatically out- put these five Status Register bits. The P/E.C. au- tomatically sets bits DQ2, DQ5, DQ6 and DQ7 ...
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... Erase Error due to the currently addressed block (when DQ5 = '1'). Program on-going or Erase Complete. Erase Suspend read on non Erase Suspend block. M36DR432A, M36DR432B Note Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. Successive reads output ...
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... M36DR432A, M36DR432B POWER CONSUMPTION Power Down The memory provides Reset/Power Down control input RPF. The Power Down function can be acti- vated only if the relevant Configuration Register bit is set to '1'. In this case, when the RPF signal is pulled at V the supply current drops to typically ...
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... Address for Primary Algorithm extended Query table Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (note: 0000h means none exists) Address for Alternate Algorithm extended Query table note: 0000h means none exists M36DR432A, M36DR432B Description 19/46 ...
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... M36DR432A, M36DR432B Table 20. CFI Query System Interface Information Offset Data V Logic Supply Minimum Program/Erase or Write voltage CCF 1Bh 0017h V Logic Supply Maximum Program/Erase or Write voltage CCF 1Ch 0022h V [Programming] Supply Minimum Program/Erase voltage PPF 1Dh 0000h V [Programming] Supply Maximum Program/Erase voltage ...
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... Number of Erase Block Regions within device bit number of Erase Block Regions Note: means no erase blocking, i.e. the device erases at once in "bulk." M36DR432A M36DR432A Erase Block Region Information 2Dh 003Eh bit where the Erase Block(s) within this Region are (z) times 256 bytes in size ...
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... M36DR432A, M36DR432B SRAM COMPONENT Device Operations The following operations can be performed using the appropriate bus cycles: Read Array, Write Ar- ray, Output Disable, Power Down (see Table 3). Read. Read operations are used to output the contents of the SRAM Array. The SRAM is in Read ...
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... Figure 6. AC Measurement Load Circuit 4ns VDD AI90206 C L includes JIG capacitance ( ° MHz) A Test Condition OUT M36DR432A, M36DR432B V DD DEVICE UNDER TEST 0.1µ 50pF Min Max 10 12 25k 25k AI90207 Unit pF pF 23/46 ...
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... M36DR432A, M36DR432B Table 24. DC Characteristics (T = –40 to 85° DDF DDS Symbol Parameter Device Input Leakage Flash & Current SRAM Output Leakage Flash & Current SRAM Flash V Standby DD I DDS Current SRAM Supply Current I Flash DDD (Reset) I Supply Current ...
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... after the falling edge of EF without increasing t GLQV M36DR432A, M36DR432B Min Typ Max 1.65 3.6 11.4 12 and . DDWS DDR Flash 100 120 Min Max Min Max 100 ...
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... M36DR432A, M36DR432B Figure 7. Flash Read AC Waveforms 26/46 ...
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... Figure 8. Flash Page Read AC Waveforms M36DR432A, M36DR432B 27/46 ...
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... M36DR432A, M36DR432B Table 26. Flash Write AC Characteristics, Write Enable Controlled (T = – ° 1.65V to 2.2V A DDF Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Write Enable Low AVWL Input Valid to Write Enable High DVWH Chip Enable Low to Write Enable Low ...
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... A0-A20 WF tWLEL GF EF DQ0-DQ15 V DDF tVDHWL Note: Address are latched on the falling edge of EF, Data is latched on the rising edge of EF. Parameter tAVAV VALID tAVEL tGHEL tELEH tDVEH M36DR432A, M36DR432B Flash 100 120 Min Max Min 100 120 ...
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... M36DR432A, M36DR432B Table 28. Flash Read and Write AC Characteristics, RPF Related (T = –40 to 85° 1.65V to 2.2V) A DDF Symbol Alt RPF High to Data Valid (Read t PHQ7V1 Mode) RPF High to Data Valid t PHQ7V2 (Power Down enabled RPF Pulse Width PLPH RP RPF Low to Reset Complete ...
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... Write Enable High to Output Valid (Program) t WHQV Write Enable High to Output Valid (Block Erase) Note: 1. All other timings are defined in Read AC Characteristics table unless otherwise specified) PPF DDF Min (2) 100,000 Parameter M36DR432A, M36DR432B Typical after (1) Typ Max 100k W/E Cycles 2.5 0.15 0 ...
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... M36DR432A, M36DR432B Figure 12. Flash Data Polling DQ7 AC Waveforms 32/46 ...
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... Figure 13. Flash Data Toggle DQ6, DQ2 AC Waveforms M36DR432A, M36DR432B 33/46 ...
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... M36DR432A, M36DR432B Figure 14. Flash Data Polling Flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 YES = DATA NO NO DQ5 = 1 YES READ DQ7 DQ7 YES = DATA NO FAIL 34/46 Figure 15. Flash Data Toggle Flowchart PASS AI90215 START READ DQ5 & DQ6 DQ6 NO = TOGGLES YES ...
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... Note: 1. Sampled only. Not 100% tested. Figure 16. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V A0-A17 DQ0-DQ15 DATA VALID Note: E1S = Low, E2S = High Low High. Parameter tAVAV VALID tAVQV tAXQX M36DR432A, M36DR432B SRAM Unit Min Max 100 ns 100 ...
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... M36DR432A, M36DR432B Figure 17. SRAM Read AC Waveforms, E1S, E2S or GS Controlled A0-A17 E1S E2S UBS, LBS GS DQ0-DQ15 Note: Write Enable (WS) = High. Figure 18. SRAM Standby AC Waveforms E1S E2S I DD 36/46 tAVAV VALID tAVQV tE1LQV tE1LQX tE2HQV tE2HQX tBLQV tBLQX tGLQV tGLQX DATA VALID tPU ...
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... E1S or WS going high low E1S and low WS. A write begins when E1S goes low and WS goes low with asserting WP is measured from the beginning of write to the end of write. WP M36DR432A, M36DR432B SRAM Unit Min Max 100 ...
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... M36DR432A, M36DR432B Figure 19. SRAM Write AC Waveforms, WS Controlled with GS Low A0-A17 tAVE1L E1S E2S UBS, LBS WS DQ0-DQ15 Note: Output Enable (GS) = Low. Figure 20. SRAM Write AC Waveforms, WS Controlled with GS High A0-A17 tAVE1L E1S E2S UBS, LBS tAVWL WS GS DQ0-DQ15 38/46 tAVAV VALID tAVWH tE1LWH tAVE2H ...
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... E2S tAVWL UBS, LBS WS DQ0-DQ15 Figure 22. SRAM Write AC Waveforms, E1S Controlled A0-A17 tAVE1L E1S E2S UBS, LBS tAVWL WS DQ0-DQ15 Note: Output Enable (GS) = High. M36DR432A, M36DR432B tAVAV VALID tE1LWH tAVWH tE2HWH tBLWH tWLWH tDVWH tWHDX DATA VALID tAVAV VALID tE1LWH tBLWH tDVE1H ...
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... M36DR432A, M36DR432B Table 33. SRAM Low V Data Retention Characteristics CCS (T = –40 to 85° 1.65V to 2.2V) A DDS Symbol Parameter I Supply Current (Data Retention) DDDR V Supply Voltage (Data Retention Chip Disable to Power Down CDR t Operation Recovery Time R Note: 1. All other Inputs V V – 0. ...
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... Device Type M36DR432 Daisy Chain -ZA = LFBGA66: 0.8mm pitch Option T = Tape & Reel Packing For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de- vice, please contact the STMicroelectronics Sales Office nearest to you. M36DR432A, M36DR432B M36DR432A 100 ZA 6 M36DR432 - 41/46 ...
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... M36DR432A, M36DR432B Table 36. Revision History Date Version 24-May-2001 -01 19-Nov-2001 -02 42/46 Revision Details First Issue LFBGA66 mechanical data updated (Table 37) ...
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... M36DR432A, M36DR432B inches Typ Min 0.0098 0.0157 0.0138 0.4724 – 0.2205 – 0.3465 – 0.3150 – 0.2205 – 0.0315 – 0.0630 – 0.0472 – ...
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... M36DR432A, M36DR432B Figure 26. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package 44/ AI90251 ...
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... Figure 27. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package) START POINT # M36DR432A, M36DR432B END POINT # AI90252 45/46 ...
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... M36DR432A, M36DR432B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...