IS61LV25616-12T Integrated Silicon Solution, IS61LV25616-12T Datasheet
IS61LV25616-12T
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IS61LV25616-12T Summary of contents
Page 1
... Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory.A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV25616 is packaged in the JEDEC standard 44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and 48-pin Mini BGA (8mm x 10mm). ...
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... IS61LV25616 PIN CONFIGURATIONS 44-Pin TSOP (Type II) and SOJ I/O0 7 I/O1 8 I/O2 9 I/O3 10 Vcc 11 GND 12 I/O4 13 I/O5 14 I/ 48-Pin mini BGA I I/O I GND I/O A17 ...
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... IS61LV25616 TRUTH TABLE WE CE Mode Not Selected X H Output Disabled Read Write ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND –0.5 to Vcc+0.5 TERM T Temperature Under Bias BIAS V Vcc Related to GND CC T Storage Temperature ...
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... IS61LV25616 DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH (1) V Input LOW Voltage IL I Input Leakage LI I Output Leakage LO Notes (min.) = –2.0V for pulse width less than 10 ns. IL POWER SUPPLY CHARACTERISTICS Symbol Parameter ...
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... IS61LV25616 READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA CE Access Time t ACE OE Access Time t DOE OE to High-Z Output t (2) HZOE OE to Low-Z Output t (2) LZOE CE to High-Z Output t (2 HZCE CE to Low-Z Output ...
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... IS61LV25616 AC WAVEFORMS READ CYCLE NO. 1 (1,2) (Address Controlled) ( ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZCE LB LZB HIGH-Z D OUT Supply Current Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB Address is valid prior to or coincident with CE LOW transition. ...
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... IS61LV25616 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time AW to Write End t Address Hold from Write End HA t Address Setup Time SA LB, UB Valid to End of Write t PWB WE Pulse Width t 1 PWE WE Pulse Width (OE = LOW) ...
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... IS61LV25616 AC WAVEFORMS (CE Controlled HIGH or LOW) WRITE CYCLE NO. 1 ADDRESS UB DATA UNDEFINED OUT D IN Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. ...
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... IS61LV25616 AC WAVEFORMS (WE Controlled HIGH During Write Cycle) WRITE CYCLE NO. 2 ADDRESS OE LOW UB DATA UNDEFINED OUT D IN (WE Controlled LOW During Write Cycle) WRITE CYCLE NO. 3 ADDRESS OE LOW CE LOW UB DATA UNDEFINED OUT D IN Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...
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... IS61LV25616 AC WAVEFORMS (LB, UB Controlled, Back-to-Back Write) WRITE CYCLE NO. 4 ADDRESS OE CE LOW WE UB HZWE D OUT DATA UNDEFINED D IN Notes: 1. The internal Write time is defined by the overlap LOW, UB and/ LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The rising or falling edge of the signal that terminates the Write ...
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... IS61LV25616-8LQI LQFP IS61LV25616-8BI Mini BGA (8mm x 10mm) 10 IS61LV25616-10TI TSOP (Type II) IS61LV25616-10KI 400-mil SOJ IS61LV25616-10LQI LQFP IS61LV25616-10BI Mini BGA (8mm x 10mm) 12 IS61LV25616-12TI TSOP (Type II) IS61LV25616-12KI 400-mil SOJ IS61LV25616-12LQI LQFP IS61LV25616-12BI Mini BGA (8mm x 10mm) 15 IS61LV25616-15TI TSOP (Type II) IS61LV25616-15KI 400-mil SOJ IS61LV25616-15LQI LQFP ...