VT86C100A ETC-unknow, VT86C100A Datasheet
VT86C100A
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VT86C100A Summary of contents
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... VIA Technologies, Inc. VT86C100A PCI F E AST THERNET DATA SHEET (Preliminary) DATE : Aug 31, 1997 VIA TECHNOLOGIES, INC. Preliminary VT86C100A C ONTROLLER ...
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... Via Technologies Incorporated. The VT86C100A may only be used to identify products of Via Technologies. All trademarks are the properties of their respective owners. Disclaimer Notice: No license is granted, implied or otherwise, under any patent or patent rights of Via Technologies ...
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... VIA Technologies, Inc. VT86C100A PCI F E AST THERNET * Single chip Fast Ethernet controller for PCI bus interface -- compliant to PCI v2.1 with optional delay transaction and sub-vendor, sub-system Provides a direct connection to PCI bus -- Supports two network ports : 10/100 M MII interface * High performance PCI mastering structure ...
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... PCI Registers FRAME# Bus State IRDY# Interface Machine TRDY# Unit Buffer DEVSEL# Mgmt. STOP# PAR PCI CFG Figure 1: Application Diagram Preliminary VT86C100A RxFIFO 2K bytes 10/100M & MAC Tx/Rx MII Protocol & TxFIFO State 2K bytes TXD[3:0], RXD[3:0], TX_EN TX_ER, RX_ER TX_CLK, RX_CLK RX_DV, CRS, COL ...
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... AD30 AD29 AD28 VDD 125 VSS AD27 AD26 128 VT86C100A Preliminary VT86C100A MA1 MA0 MD7 MD6 MD5 VSS VDD 55 MD4 MD3 MD2 MD1 MD0 50 BPRD# ECS VSS VDD AD0 ...
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... PCICLK provides timing for all transactions on PCI and is an input pin to every PCI device. INTA asynchronous signal which is used to request an interrupt When PCIRST# is asserted low, the VT86C100A chip performs an internal system hardware reset. PCIRST# may be asynchronous to CLK when asserted or deasserted recommended that the deassertion be synchronous to guarantee clean and bounce free edge ...
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... For data phases PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. Bus grant asserts to indicate to the VT86C100A that access to the bus is granted. Bus request is asserted by the bus master indicate to the bus arbiter that it wants to use the bus ...
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... G 41,48,57 ,66,75,7 7,88,98, 107,116, 126 Preliminary VT86C100A Bootrom address line [0-15] General purpose input and output 1 : usually as Magic key interrupt line General purpose input and output 2, this pin usually as link change status from external PHY device. Positive 5V Supply: Supply power to Internal digital logic, Digital I/O pads, and TD, TX pads. Double bonding may be required. ...
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... ENERAL ESCRIPTION The VT86C100A Rhine ACPI PCI bus master 100 M FAST Ethernet controller is CMOS VLSI designed for easy implementation of CSMA/CD IEEE 802.3u 100M local area networks. Significant features include: twisted-pair interface, PCI Plug&Play compatibility, 32 bit bus mastering, powerful buffer management and Early Interrupt Receive/Transmit ...
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... IRECT ROGRAMMING OF The VT86C100A features a easy way to program external EEPROM in-situ. When the RESET is active and if the upper byte of 0FH on EEPROM is not 73H, the EEPR bit will not be set to indicate that the current EEPROM has not been programmed yet. This will allow the VT86C100A to enter Direct Programming mode if EELOAD is also set ...
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... VIA Technologies, Inc. EEPROM has been programmed and verified (remember to program the upper byte of 0EH & 0FH with 73H), the user must give VT86C100A a power-on reset to return to normal operation and to read in the new data. The Direct Programming mode is mainly used for production to program every bit of the EEPROM. Once the ...
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... Register A to diagnostic mode then set the Power-on bit of the diagnostic port to "on." When the VT86C100A is in Power down mode, all power to the PCI interface is cut off and the chip clock is stopped. Other registers are read only. Only the diagnostic port is read/writeable. ...
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... UFFER ANAGEMENT The VT86C100A provides an simply and effective buffer management and host communication method through the PCI Bus mastering : There are two descriptor lists, one for receive and one for transmit. The base of these two list are pointed into the CRDA (18h) and CTDA (1ch) registers. ...
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... RDES0 contain the received frame status, the frame length and the descriptor ownership information. Owner : This bit control by driver identify this descriptor own by VT86C100A controller, 0 means this descriptor be a free descriptor; Driver must set this bit be zero when initialed. Extend Frame Length : Extend byte count for no-normal size Ethernet frame Frame Length : Received frame length, Received OK : The VT86C100A received a good packet from network ...
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... FIFO under-flow - excessive collision (ABT) - late collision (OWC) - carrier sense lost (CRS) 14 JAB Jabber : This bit will set high if Jabber condition happens. Writing to this bit has no effect System Error : VT86C100A MAC experience error master abort, target abort, parity error. 12 Reserve 11 Reserve 1 (RDES1) 23 ...
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... Collision retry count : this 4-bits counter indicates the number of collisions that occurred FIFO under-flow : this bit set indicates that the transmitter aborted by transmit FIFO encountered an empty while transmitting a frame. Deferred: When set, indicates that the VT86C100A had to defer while ready to transmit a frame because carrier was asserted. 6.2. ...
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... VIA Technologies, Inc. 6.3.1 Multiple Chained buffer structure The VT86C100A can support multiple chain buffer for direct map to OS`s data buffer. The VT86C100A bus mastering module will direct move the data from network to the OS`s data buffer or direct transmit the data in OS`s buffer onto network not necessary move to a temperate data buffer. But the data buffer must be double word aligned ...
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... VIA Technologies, Inc. 6.3.2 Interrupt Control The VT86C100A can controllable the receive descriptors and transmit descriptor for what the interrupt occurred. The IC bit (DES1[23]) be set 1, the receive or transmit interrupt will be generate the interrupt no matter the frame been complete received or transmitted. This feature will enable the OS pre-fetch the frame header or saving the interrupt service overload ...
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... BCR1 6c 70 MII DATA REG 74 78 CFGD Tally counter_CRC 7c Preliminary VT86C100A EGISTERS byte2 byte1 byte0 PAR1/KEY1 PAR0/KEY0 RCR PAR5/KEY5 PAR4/KEY4 CR1 CR0 IMR0 ISR1 ISR0 MAR2 MAR1 MAR0 MAR6 MAR5 MAR4 Curr Rx Desc Addr Curr Tx Desc Addr ...
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... AB20 AB19 AB30 AB29 AB28 AB27 MPO0 PHYAD PHYAD 4 3 LEDPO MFDC PHYOP MIIERR L T REQOP CRFT2 CRFT1 CRFT0 T Preliminary VT86C100A Bit 1 Bit 0 Read/ Write MT10E MT10EOE 78H NO MRWA LATMEM 79H IT BPS1 BPS0 7AH MBA BAKOPT 7BH Bit 2 Bit 1 Bit 0 DA2 ...
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... CFGC R/W 7BH CFGD R/W GPIOE N 7CH MPAC0 R/W CD7 7DH MPAC1 R/W CD15 7EH CRCC0 R/W CD7 7FH CRCC1 R/W CD15 Preliminary VT86C100A CTSF CTF1 CTF0 RCMD WCMD MDPM MOUT MSRCE MDON MAD4 MAD3 N E EMBP LOAD DPM ECS FCOL BKOFF TSTOV TSTUD F F JUMPE ...
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... BPS3 Configuration Register D (0x7B) 0 BAKOPT n/a Preliminary VT86C100A GPIO2OE : Output enable of GPIO2 pin GPIO2O : Output to GPIO2 pin GPIO2I : GPIO2 input status AUTOOPT : enable receive event auto transmit descriptor polling MMIEN : Memory mapped IO enable, accept memory command JUMPER : Jumper mode to select PHY and operation mode ...
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... VIA Technologies, Inc. 4 MAGIC n/a 7 GPIOEN n/a Preliminary VT86C100A MBA : Modify back off algorithm CAP : Capture effect back off CRADOM : Random back off algorithm MAGIC : Turn on Magic key DIAG : GPIOEN : Turn on GPIO2 input status change monitor ...
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... This bit indicates that VT86C100A enter the start command. 0 INIT Initialize Start : When set on the VT86C100A start to set its bus master register the start CR1: Command Register 1 (09H; Type=R/W) This register is used to select register pages, enable or disable remote DMA operation and issue commands ...
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... Back-off priority selection : change the back off algorithm as National specification Loopback mode select for transmit : 2-1 LB[1- Normal 0 1 Internal loopback 1 0 ENDEC loopback for 10Base-T or MII loopback 1 1 223 loopback or others 0 - Reserved. Preliminary VT86C100A Description RTF0 Threshold 0 64 bytes 128 1 ...
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... EEPROM Configuration and status Register Group EECSR EEPROM Command Status Register (74H, Type=R/W) EEPROM programming status 6 EMBP EEPROM embedded program enable, the VT86C100A will set this bit to zero after programming complete. Dynamic reload EEPROM content, the PAR[5-0] will be update 5 LOAD 4 ...
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... GPIO1 pin output active high; set as '0', the GPIO1 pin output active low. 6 res Reserve 5 MFDC MFDC : Accelerate the MDC speed when VT86C100A enter MII auto polling; MFDC set as '0', MDC be normal speed; or MFDC set as '1' , MDC be 4 times speed. 4 PHYOPT PHYOPT : set 1 use default external PHY device address as 0001 3 MIIERR MIIERR : PHY device coding error by insert RX_ERR, write to clear it ...
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... MII management port polling timer interval, timer unit be MDC clock cycle MPO1 MPO0 res 4-0 PHYAD[ PHY[4-0] : external PHY device address , these register bytes stored from EEPROM loading when power up or EEPROM auto-reloading or can be programmed by software, 4-0] default as (00001)b Preliminary VT86C100A clock 1024 512 128 64 ...
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... VIA Technologies, Inc. [This page left to blank] Preliminary VT86C100A ...
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... A59 C5 . B60 A60 C6 . B61 A61 C7 . B62 A62 C12 .1u C13 .1u PCI_CONB PCI_CONA C11 .1u C14 .1u C15 .1u Preliminary VT86C100A PCIVCC MA[15: MD[7: VT3043E AD31 121 90 MCRS AD31 MCRS 122 91 AD30 MCOL AD30 MCOL 123 ...
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... ANAGND_D 88 RESET HDRST CGMGND_D R51 DP83840A 33 Physical Layer L2 C18 C19 C20 47uH .1u .1u .1u .1u ANAVCC C40 C16 22u .001u C32 C33 .1u .1u .1u Preliminary VT86C100A R78 D9 510 RN2 PWR 510 LED_TX LED_RX LED_LK LED_P/F ...
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... R67 A9 21 4.7K 4.7K MA10 A10 23 MA11 A11 R64 MA12 2 A12 0 26 MA13 A13 MA14 27 A14 1 MA15 A15 R65 -BPRD OE 27512 Preliminary VT86C100A RP6 J2 RP5 1 MD7 MD6 MD5 MD4 MD3 MD2 MD1 13 14 ...