PL-3507 Prolific Technology Inc., PL-3507 Datasheet
PL-3507
Available stocks
Related parts for PL-3507
PL-3507 Summary of contents
Page 1
... PL-3507 (For Chip Rev D) Hi-Speed USB & IEEE 1394 Combo to IDE Bridge Controller Product Datasheet Document Revision: 1.1 Document Release: August 28, 2007 Prolific Technology Inc. 7F, No. 48, Sec. 3, Nan Kang Rd. Nan Kang, Taipei 115, Taiwan, R.O.C. Telephone: +886-2-2654-6363 Fax: +886-2-2654-6161 E-mail: sales@prolific.com.tw Website: http://www ...
Page 2
... Copyrights Copyright © 2007 Prolific Technology Inc., All rights reserved. No part of this document may be reproduced or transmitted in any form by any means without the express written permission of Prolific Technology Inc. PL-3507D Product Datasheet - 2 - Revised Date: August 28, 2007 ds_pl3507D_v1.1.doc ...
Page 3
... Update datasheet to add Chip Rev 2D information 1.0C Section 3: Modify Functional Block Diagram 1.0B Note: Chip Rev 1D does not support internal ROM code and requires external Flash to load firmware. 1.0A PL-3507 (Chip Rev D) Datasheet – Formal Release 0.9A PL-3507 (Chip Rev D) Datasheet – Preliminary Release PL-3507D Product Datasheet Description - 3 - Revised Date: August 28, 2007 ds_pl3507D_v1 ...
Page 4
... External Flash Memory Programming Control..................................................... 16 8.0 DC CHARACTERISTICS ................................................................................17 8.1 Absolute Maximum Ratings ................................................................................. 17 8.2 Recommended Operating Conditions.................................................................. 17 8.3 Leakage Current and Capacitance ...................................................................... 17 8.4 Recommended Supply Voltage & Operating Junction Temperature Ranges ...... 18 9.0 ORDERING INFORMATION ...........................................................................18 10.0 OUTLINE DIAGRAM.......................................................................................19 PL-3507D Product Datasheet Table of Contents - 4 - Revised Date: August 28, 2007 ds_pl3507D_v1.1.doc Document Version 1.1 ...
Page 5
... Figure 3-1 Block Diagram of PL-3507D (Chip Rev D) .............................................................. 8 Figure 4-1 System Application Diagram of PL-3507D (Chip Rev D)......................................... 9 Figure 5-1 Pin Assignment Outline of PL-3507 (Chip Rev D) ................................................. 10 Figure 10-1 Outline Diagram of PL-3507 LQFP128................................................................ 19 Table 6-1 Pin Assignment & Description [GPIO (ATA/ATAPI Interface)] ................................. 11 Table 6-2 Pin Assignment & Description [1394 PHY-Link Interface] ....................................... 12 Table 6-3 Pin Assignment & ...
Page 6
... FireWIRE and i.LINK 1394 Compliant Logo (TA ID #200404004) USB-IF Hi-Speed Logo Certified (TID No. 40002614) Backward Pin-to-Pin Compatible with PL-3507 Chip Rev C (contact Prolific FAE) Inexpensive LQFP package type: LQFP128pin (14x14mm) Note: Chip Rev 1D does not have an internal ROM code and requires an external Flash to load the firmware ...
Page 7
... Product Overview The PL-3507 is a high performance combo bridge solution for connecting USB 2.0 and 1394 to ATA or ATAPI data storage devices, e.g. hard disk drives, CD-ROM, CD-R, CD-RW and DVD. The USB interface of PL-3507 supports USB 1.1 or USB 2.0 specifications to allow connections to host computer via USB port at maximum data transfer rate 480 Mbps. ...
Page 8
... DIO[7:0] LREQ 1394 SBP2 LPS Link Layer LINKON SCLK DP USB UTMI & DN USB Link Layer Program SRAM Figure 3-1 Block Diagram of PL-3507D (Chip Rev D) PL-3507D Product Datasheet FIFO ATA/ATAPI Interface MMU Program 8032 ROM - 8 - Revised Date: August 28, 2007 ds_pl3507D_v1.1.doc DMA_DIO[15:0] GP0[7:0] GP1[7:0] Document Version 1 ...
Page 9
... System Application Diagram ATA/ATAPI signals ADDR[14:0] ROM/ FLASH DATA[7:0] Figure 4-1 System Application Diagram of PL-3507D (Chip Rev D) PL-3507D Product Datasheet IDE SLOT Regulator P2[6:0],P0[7:0] PL3507 P1[7:0] 1394 PHY-LINK interface signals 1394 PHY - 9 - Revised Date: August 28, 2007 ds_pl3507D_v1.1.doc 3.3V USB_DP USB_DM TPA0 TPB0 TPA1 TPB1 ...
Page 10
... Pin Assignment Outline Figure 5-1 Pin Assignment Outline of PL-3507 (Chip Rev D) PL-3507D Product Datasheet - 10 - Revised Date: August 28, 2007 ds_pl3507D_v1.1.doc Document Version 1.1 ...
Page 11
... GP0[4] : CSJ1 GP0[5] : PROM_WR GP0[6] : PROM_CE GP0[7] : USBVCC DMA_DIO[0:7] 107~114 DMA_DIO[8:15] 116~123 PL-3507D Product Datasheet I/O 124 I/O (O) Reset signal of ATA/ATAPI devices (DIOWJ): For modes other than ultra DMA burst in/out, this is a write strobe signal. 125 I/O (O) (STOP): For ultra DMA burst in/out, host can use this signal to stop ultra DMA burst transfer ...
Page 12
... Table 6-4 Pin Assignment & Description [USB Interface] Name Pin No. USB_DP USB_DM USB_RREF USB_RPU USB_DPRS USB_DMRS XSCI XSCO PL-3507D Product Datasheet I/O I/O 1394 PHY-LINK control bus I/O 1394 PHY-LINK data bus 53 O 1394 Link layer request indicator 44 I 1394 System clock supplied by PHY. 49.152MHz ...
Page 13
... GND 30, 31, 63, 89, 127, 128 AGND 93, 97, 102 6.8 Extra GPIO Pins Table 6-8 Pin Assignment & Description [Extra GPIO Pins] Name Pin No. EGPIO[0:5] 81~86 PL-3507D Product Datasheet I Reset signal, active low 87 I Program memory test mode I 00: Normal operation mode 74 I ...
Page 14
... Mbytes/sec. When connecting to host computers through USB cable, host computer will get device descriptor from the PL-3507 in order to be recognized as a mass storage class device, and then the host can start to transfer data to/from ATA/ATAPI devices through the PL-3507. PL-3507D Product Datasheet ...
Page 15
... EGPIO[5] is connected to internal USB remote wake-up port that can wake-up the PL-3507 from sleep mode. All the sources of interrupt 1 can wake-up the PL-3507 from sleep mode no matter how PL-3507 went to sleep either from USB or 1394. ...
Page 16
... FT8032 for intended data and flash control register for read/write control. The starting address of USB firmware code should be located at “0000h” in the external flash, and 1394 firmware code should be at “8000h”. PL-3507D Product Datasheet - 16 - Revised Date: August 28, 2007 ds_pl3507D_v1 ...
Page 17
... C IN Output Capacitance C OUT Bi-directional Buffer C BID Capacitance Note: The capacitances listed above do not include PAD capacitance. One can estimate pin capacitance by adding pad’s capacitance that is about 0.1 pf and the package capacitance. PL-3507D Product Datasheet Table 8-1 Absolute Maximum Ratings PARAMETER MIN 2.25 3.0 3.0 3.0 2. ...
Page 18
... Note: The chip version can be found on the chip-marking showing: “YYWW2D” (datecode + chip version). Where: YY – last two digits of the year WW – week of the year 2D – chip version Example: “06102D” – means year 2006 + week no chip version. PL-3507D Product Datasheet Conditions MIN CMOS/LVTTL CMOS/LVTTL 2.0 ...
Page 19
... Outline Diagram Figure 10-1 Outline Diagram of PL-3507 LQFP128 PL-3507D Product Datasheet - 19 - Revised Date: August 28, 2007 ds_pl3507D_v1.1.doc Document Version 1.1 ...