VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 
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I/O Offset 3B-38 - GP Timer Reload Enable .................. RW
All bits in this register default to 0 on power up.
..........................................always read 0
31-8 Reserved
7
GP1 Timer Reload on KBC Access
0
Normal GP1 Timer Operation................default
1
Setting of KBC_STS causes the GP1 timer to
reload.
6
GP1 Timer Reload on Serial Port Access
0
Normal GP1 Timer Operation ...............default
1
Setting of COMA_STS or COMB_STS causes
the GP1 timer to reload.
5
Reserved
..........................................always read 0
4
GP1 Timer Reload on VGA Access
0
Normal GP1 Timer Operation ...............default
1
Setting of VGA_STS causes the GP1 timer to
reload.
3
GP1 Timer Reload on IDE/Floppy Access
0
Normal GP1 Timer Operation ...............default
1
Setting
of
FDC_STS,
PIDE_STS causes the GP1 timer to reload.
2
GP3 Timer Reload on GPIO Range 1 Access
0
Normal GP3 Timer Operation ...............default
1
Setting of GR1_STS causes the GP3 timer to
reload.
1
GP2 Timer Reload on GPIO Range 0 Access
0
Normal GP2 Timer Operation ...............default
1
Setting of GR0_STS causes the GP2 timer to
reload.
0
GP0 Timer Reload on Primary Activity
0
Normal GP0 Timer Operation ...............default
1
Setting of PACT_STS causes the GP0 timer to
reload. Primary activities are enabled via the
Primary Activity Detect Enable register (offset
37-34) with status recorded in the Primary
Activity Detect Status register (offset 33-30).
Revision 1.71 June 9, 2000
I/O Offset 40 – Extended I/O Trap Status ................... RWC
7-5
Reserved
4
BIOS Write Enable Status................... (BWR_STS)
(Function 0 Rx40[7])
3-2
Reserved
1
GPIO Range 3 Access Status .............. (GPR3_STS)
0
GPIO Range 2 Access Status .............. (GPR2_STS)
I/O Offset 42 – Extended I/O Trap Enable ..................... RW
7-5
Reserved
4
SMI on BIOS Write............................... (BWR_EN)
0
1
3-2
Reserved
1
SMI on GPIO Range 3 Access..............(GPR3_EN)
0
1
0
SMI on GPIO Range 2 Access..............(GPR2_EN)
0
1
SIDE_STS,
or
-97-
VT82C686B
......................................... always read 0
......................................... always read 0
......................................... always read 0
Disable................................................... default
Enable
......................................... always read 0
Disable................................................... default
Enable
Disable................................................... default
Enable
Power Management I/O-Space Registers