VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 


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Legacy Power Management Timers
In addition to the ACPI power management timer, the
VT82C686B includes the following four legacy power
management timers:
GP0 Timer: general purpose timer with primary event
GP1 Timer: general purpose timer with peripheral event
reload
Secondary Event Timer: to monitor secondary events
Conserve Mode Timer: Hardware-controlled return to
standby
The normal sequence of operations for a general purpose timer
(GP0 or GP1) is to
1) First program the time base and timer value of the initial
count (register GP_TIM_CNT).
2) Then activate counting by setting the GP0_START or
GP1_START bit to one: the timer will start with the
initial count and count down towards 0.
3) When the timer counts down to zero, an SMI will be
generated if enabled (GP0TO_EN and GP1TO_EN in the
GBL_EN register) with status recorded (GP0TO_STS and
GP1TO_STS in the GBL_STS register).
4) Each timer can also be programmed to reload the initial
count and restart counting automatically after counting
down to 0. This feature is not used in standard VIA
BIOS.
The GP0 and GP1 timers can be used just as the general
purpose timers described above. However, they can also be
programmed to reload the initial count by system primary
events or peripheral events thus used as primary event (global
standby) timer and peripheral timer, respectively.
secondary event timer is solely used to monitor secondary
events.
System Primary and Secondary Events
Primary system events are distinguished in the PRI_ACT_STS
and PRI_ACT_EN registers:
Bit Event
Trigger
7 Keyboard Access
I/O port 60h
6 Serial Port Access
I/O ports 3F8h-3FFh, 2F8h-2FFh,
3E8h-3EFh, or 2E8h-2EFh
5 Parallel Port Access I/O ports 378h-37Fh or 278h-27Fh
4 Video Access
I/O ports 3B0h-3DFh or memory
A/B segments
3 IDE/Floppy Access
I/O ports 1F0h-1F7h, 170h-177h,
or 3F5h
2 Reserved
1 Primary Interrupts
Each channel of the interrupt
controller can be programmed to
be
a
interrupt
0 ISA Master/DMA Activity
Each category can be enabled as a primary event by setting the
corresponding bit of the PRI_ACT_EN register to 1.
Revision 1.71 June 9, 2000
enabled, the occurrence of the primary event reloads the GP0
timer if the PACT_GP0_EN bit is also set to 1. The cause of
the timer reload is recorded in the corresponding bit of
PRI_ACT_STS register while the timer is reloaded. If no
enabled primary event occurs during the count down, the GP0
timer will time out (count down to 0) and the system can be
programmed (setting the GP0TO_EN bit in the GBL_EN
register to one) to trigger an SMI to switch the system to a
power down mode.
The VT82C686B distinguishes two kinds of interrupt requests
as far as power management is concerned: the primary and
secondary interrupts.
occurrence of a primary interrupt demands that the system be
restored to full processing capability. Secondary interrupts,
however, are typically used for housekeeping tasks in the
background unnoticeable to the user. The VT82C686B allows
each channel of interrupt request to be declared as either
primary, secondary, or ignorable in the PIRQ_CH and
SIRQ_CH registers. Secondary interrupts are the only system
secondary events defined in the VT82C686B.
Like primary events, primary interrupts can be made to reload
the GP0 timer by setting the PIRQ_EN bit to 1. Secondary
interrupts do not reload the GP0 timer. Therefore the GP0
timer will time out and the SMI routine can put the system into
power down mode if no events other than secondary interrupts
are happening periodically in the background.
Primary events can be programmed to trigger an SMI (setting
of the PACT_EN bit). Typically, this SMI triggering is turned
off during normal system operation to avoid degrading system
performance. Triggering is turned on by the SMI routine
before entering the power down mode so that the system may
The
be returned to normal operation at the occurrence of primary
events. At the same time, the GP0 timer is reloaded and the
count down process is restarted.
Peripheral Events
Primary and secondary events define system events in general
and the response is typically expressed in terms of system
events. Individual peripheral events can also be monitored by
the VT82C686B through the GP1 timer. The following four
categories of peripheral events are distinguished (via register
GP_RLD_EN):
Bit-7
Bit-6
Bit-4
Bit-3
The four categories are subsets of the primary events as
defined in PRI_ACT_EN and the occurrence of these events
can be checked through a common register PRI_ACT_STS.
As a peripheral timer, GP1 can be used to monitor one (or
primary
or
secondary
more than one) of the above four device types by programming
the corresponding bit to one and the other bits to zero. Time
out of the GP1 timer indicates no activity of the corresponding
device type and appropriate action can be taken as a result.
If
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VT82C686B
Like other primary events, the
Keyboard Access
Serial Port Access
Video Access
IDE/Floppy Access
Functional Descriptions