Revision 1.71 June 9, 2000
(see pin list)
Address/Data Bus. The standard PCI address and data lines. The address is driven with
FRAME# assertion and data is driven or received in following cycles.
Command/Byte Enable. The command is driven with FRAME# assertion. Byte enables
corresponding to supplied or requested data are driven on following clocks.
Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that
one more data transfer is desired by the cycle initiator.
Initiator Ready. Asserted when the initiator is ready for data transfer.
Target Ready. Asserted when the target is ready for data transfer.
Stop. Asserted by the target to request the master to stop the current transaction.
Device Select. The VT82C686B asserts this signal to claim PCI transactions through
positive or subtractive decoding.
VT82C686B-initiated transaction and is also sampled when decoding whether to
subtractively decode the cycle.
Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
System Error. SERR# can be pulsed active by any PCI device that detects a system error
generate an NMI to the CPU.
Initialization Device Select. IDSEL is used as a chip select during configuration read and
write cycles. Connect this pin to AD18 using a 100
PCI Interrupt Request. These pins are typically connected to the PCI bus INTA#-
INTD# pins as follows:
PCI Request. This signal goes to the North Bridge to request the PCI bus.
PCI Grant. This signal is driven by the North Bridge to grant PCI access to the
PCI Clock. PCLK provides timing for all transactions on the PCI Bus.
PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be stopped
(high) or running (low). The VT82C686B drives this signal low when the PCI clock is
running (default on reset) and releases it when it stops the PCI clock. External devices
may assert this signal low to request that the PCI clock be restarted or prevent it from
stopping. Connect this pin to ground using a 100
Refer to the “PCI Mobile Design Guide” and the VIA “Apollo MVP4 Design Guide” for
PCI Reset. Active low reset signal for the PCI bus. The VT82C686B will assert this pin
during power-up or from the control register.
PCI Slot 1
PCI Slot 2
PCI Slot 3
PCI Slot 4
Table 1. Pin Descriptions
Upon sampling SERR# active, the VT82C686B can be programmed to
PCI Bus Interface
As an input, DEVSEL# indicates the response to a
resistor if the function is not used.