VT82C686B ETC-unknow, VT82C686B Datasheet - Page 45

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VT82C686B

Manufacturer Part Number
VT82C686B
Description
Manufacturer
ETC-unknow
Datasheet
7HFKQRORJLHV ,QF
Register Descriptions
Legacy I/O Ports
This group of registers includes the DMA Controllers,
Interrupt Controllers, and Timer/Counters as well as a number
of miscellaneous ports originally implemented using discrete
logic on original PC/AT motherboards. All of the registers
listed are integrated on-chip. These registers are implemented
in a precise manner for backwards compatibility with previous
generations of PC hardware. These registers are listed for
information purposes only.
Detailed descriptions of the
actions and programming of these registers are included in
numerous
industry
publications
information here is beyond the scope of this document). All of
these registers reside in I/O space.
Revision 1.71 June 9, 2000
Port 61 - Misc Functions & Speaker Control ................. RW
7
6
5
4
(duplication
of
that
3
2
1
0
Port 92h - System Control ................................................ RW
7-6
5-4
3
2
1
0
-39-
Reserved
........................................always reads 0
IOCHCK# Active .................................................RO
This bit is set when the ISA bus IOCHCK# signal is
asserted. Once set, this bit may be cleared by setting
bit-3 of this register.
Bit-3 should be cleared to
enable recording of the next IOCHCK#. IOCHCK#
generates NMI to the CPU if NMI is enabled.
Timer/Counter 2 Output......................................RO
This bit reflects the output of Timer/Counter 2
without any synchronization.
Refresh Detected...................................................RO
This bit toggles on every rising edge of the ISA bus
REFRESH# signal.
IOCHCK# Disable...............................................RW
0
Enable IOCHCK# assertions ................. default
1
Force IOCHCK# inactive and clear any
“IOCHCK# Active” condition in bit-6
Reserved
........................................RW, default=0
Speaker Enable ....................................................RW
0
Disable................................................... default
1
Enable Timer/Ctr 2 output to drive SPKR pin
Timer/Counter 2 Enable .....................................RW
0
Disable................................................... default
1
Enable Timer/Counter 2
Hard Disk Activity LED Status
0
Off
.................................................... default
1-3 On
Reserved
........................................always reads 0
Power-On Password Bytes Inaccessable ..default=0
Reserved
........................................always reads 0
A20 Address Line Enable
0
A20 disable / forced 0 (real mode) ........ default
1
A20 address line enable
High Speed Reset
0
Normal
1
Briefly pulse system reset to switch from
protected mode to real mode
Register Descriptions - Legacy I/O Ports
VT82C686B

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