VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 


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Function 0 Registers - PCI to ISA Bridge
All registers are located in the function 0 PCI configuration
space of the VT82C686B. These registers are accessed
through PCI configuration mechanism #1 via I/O address
CF8/CFC.
PCI Configuration Space Header
Offset 1-0 - Vendor ID = 1106h ......................................... RO
Offset 3-2 - Device ID = 0686h .......................................... RO
Offset 5-4 - Command ....................................................... RW
15-8 Reserved
........................................ always reads 0
7
Address / Data Stepping
0
Disable
1
Enable ....................................................default
6-4
Reserved
........................................ always reads 0
3
Special Cycle Enable .....Normally RW†, default = 0
2
Bus Master ........................................ always reads 1
1
Memory Space.................. Normally RO†, reads as 1
0
I/O Space
...................... Normally RO†, reads as 1
† If the Rx46[4] test bit is set, access to bits 0, 1, and 3 above
is reversed: bit-3 becomes read only (reading back 1) and bits
0-1 become read / write (with a default of 1).
Offset 7-6 - Status ........................................................... RWC
15
Detected Parity Error .................... write one to clear
14
Signalled System Error...................... always reads 0
13
Signalled Master Abort ................. write one to clear
12
Received Target Abort .................. write one to clear
11
Signalled Target Abort .................. write one to clear
10-9 DEVSEL# Timing .................... fixed at 01 (medium)
8
Data Parity Detected.......................... always reads 0
7
Fast Back-to-Back.............................. always reads 0
6-0
Reserved
........................................ always reads 0
Offset 8 - Revision ID = nn ................................................ RO
7-0
Revision ID
0x VT82C686
1x VT82C686A
4x VT82C686B
Offset 9 - Program Interface = 00h ................................... RO
Offset A - Sub Class Code = 01h ....................................... RO
Offset B - Class Code = 06h ............................................... RO
Offset E - Header Type = 80h ............................................ RO
7-0
Header Type Code .........80h (Multifunction Device)
Offset F - BIST = 00h ......................................................... RO
Offset 2F-2C - Subsystem ID ............................................. RO
Use offset 70-73 to change the value returned.
Revision 1.71 June 9, 2000
ISA Bus Control
Offset 40 - ISA Bus Control ............................................. RW
7
ISA Command Delay
0
Normal................................................... default
1
Extra
6
Extended ISA Bus Ready
0
Disable................................................... default
1
Enable
5
ISA Slave Wait States
0
4 Wait States.......................................... default
1
5 Wait States
4
Chipset I/O Wait States
0
2 Wait States.......................................... default
1
4 Wait States
3
I/O Recovery Time
0
Disable................................................... default
1
Enable
2
Extend-ALE
0
Disable................................................... default
1
Enable
1
ROM Wait States
0
1 Wait State ........................................... default
1
0 Wait States
0
ROM Write
0
Disable................................................... default
1
Enable
Offset 41 - ISA Test Mode ................................................ RW
Bus Refresh Arbitration (do not program) default=0
7
6
I/O Recovery Time
0
Normal (13 BCLKs) .............................. default
1
Medium (8 BCLKs)
5
Port 92 Fast Reset
0
Disable................................................... default
1
Enable
A20G Emulation (do not program) .............default=0
4
3
Double DMA Clock
0
Disable (DMA Clock = ½ ISA Clock)... default
1
Enable (DMA Clock = ISA Clock)
This function can be enabled for external ISA devices
(e.g., advanced Super-IO or FIR controllers) which
support 8MHz DMA channels. However, if this bit is
set to 1, then all DMA channels will be 8 MHz. If
this bit is set to 1 and Rx45[n] is set to 1, then ISA
DMA channel ‘n’ will be 16 MHz.
typically this bit is set to 0 and the appropriate bits of
Rx45 should be set to 1 to enable 8 MHz DMA clock
only for specific channels that support the higher rate.
2
SHOLD Lock During INTA (do not program) def=0
Refresh Request Test Mode (do not program).def=0
1
0
ISA Refresh
0
Disable................................................... default
1
Enable
This bit should be set to 1 for ISA compatibility.
-55-
Function 0 Registers - PCI to ISA Bridge
VT82C686B
Therefore,