VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Page 71
72
Page 72
73
Page 73
74
Page 74
75
Page 75
76
Page 76
77
Page 77
78
Page 78
79
Page 79
80
Page 80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Page 76/128

Download datasheet (2Mb)Embed
PrevNext
7HFKQRORJLHV ,QF
IDE-Controller-Specific Confiiguration Registers
Offset 40 - Chip Enable (00h) ........................................... RW
7-4
Reserved
........................................ always reads 0
Reserved (Do Not Program)...........R/W, default = 0
3-2
1
Primary Channel Enable........ default = 0 (disabled)
Secondary Channel Enable .... default = 0 (disabled)
0
Offset 41 - IDE Configuration I (06h) ............................. RW
7
Primary IDE Read Prefetch Buffer
0
Disable ...................................................default
1
Enable
6
Primary IDE Post Write Buffer
0
Disable ...................................................default
1
Enable
5
Secondary IDE Read Prefetch Buffer
0
Disable ...................................................default
1
Enable
4
Secondary IDE Post Write Buffer
0
Disable ...................................................default
1
Enable
3-2
Reserved
........................................ always reads 0
Reserved (Do Not Program)...................... default=1
1
0
Reserved
........................................ always reads 0
Offset 42 - IDE Configuration II (09h) ............................ RW
7-2
Reserved (Do Not Program)........ default = 000010b
DEVSEL# Timing Select ..................... default = 01b
1-0
(also reflected in Rx07)
Offset 43 - FIFO Configuration (0Ah) ............................. RW
7-4
Reserved
........................................ always reads 0
3-2
Threshold for Primary Channel
00 0
01 1/4
10 1/2
.....................................................default
11 3/4
1-0
Threshold for Secondary Channel
00 0
01 1/4
10 1/2
.....................................................default
11 3/4
Revision 1.71 June 9, 2000
Offset 44 - Miscellaneous Control 1 (68h) ...................... RW
7
Reserved
........................................always reads 0
6
Master Read Cycle IRDY# Wait States
0
0 wait states
1
1 wait state ............................................. default
5
Master Write Cycle IRDY# Wait States
0
0 wait states
1
1 wait state ............................................. default
4
PIO Read Prefetch Byte Counter
0
Disable................................................... default
1
Enable
3
Bus Master IDE Status Register Read Retry
Retry bus master IDE status register read when
master write operation for DMA read is not complete
0
Disable
1
Enable .................................................... default
2
Packet Command Prefetching
0
Disable................................................... default
1
Enable
1
Reserved
........................................always reads 0
0
UltraDMA Host Must Wait for First Strobe
Before Termination
0
Enable .................................................... default
1
Disable
Offset 45 - Miscellaneous Control 2 (00h) ...................... RW
7
Reserved
........................................always reads 0
6
Interrupt Steering Swap
0
Don’t swap channel interrupts ............... default
1
Swap interrupts between the two channels
5
Reserved
........................................always reads 0
4
Rx3C Write Protect
0
Disable................................................... default
1
Enable
3
Memory Read Multiple Command
0
Disable................................................... default
1
Enable
2
Memory Read and Invalidate Command
0
Disable................................................... default
1
Enable
........................................always reads 0
1-0
Reserved
Offset 46 - Miscellaneous Control 3 (C0h) ..................... RW
7
Primary Channel Read DMA FIFO Flush
0
Disable
1
Enable FIFO flush for Read DMA when
interrupt asserts primary channel. .......... default
6
Secondary Channel Read DMA FIFO Flush
0
Disable
1
Enable FIFO flush for Read DMA when
interrupt asserts secondary channel........ default
5-0
Reserved
........................................always reads 0
-70-
Function 1 Registers - Enhanced IDE Controller
VT82C686B