VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 


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Offset 54 – Power Well Control ...................................... WO
7
SMBus Clock Select
0
SMBus Clock from 14.31818 MHz Divider def
1
SMBus Clock from RTC 32.768 KHz
6
STR Power Well Output Gating
0
Disable ...................................................default
1
Enable
5
SUSC# = 0 for STR
0
Disable ...................................................default
1
Enable
4
SUSST1# / GPO3 Select (Pin V10)
0
SUSST1#................................................default
1
GPO3
3
GPO2 / SUSB# Select (Pin W9)
0
SUSB#....................................................default
1
GPO2
Before chip rev C, this definition was reversed
See also Function 0 Rx74[7] and 77[4]
2
GPO1 / SUSA# Select (Pin V9)
0
SUSA# ...................................................default
1
GPO1
Before chip rev C, this definition was reversed
See also Function 0 Rx74[7] and 77[4]
1-0
GPO0 (SLOWCLK) Output Selection (Pin T8)
00 From GPO0 (PMU I/O Rx4C[0])...........default
01 1 Hz
10 4 Hz
11 16 Hz
Revision 1.71 June 9, 2000
Offset 55 – USB Wakeup .................................................. RW
7-3
Reserved
........................................always reads 0
2
Deassert SUSST1# Before PWRGD Rising for S5
Wakeup
0
Disable................................................... default
1
Enable
........................................always reads 0
1
Reserved
0
USB Wakeup for STR/STD/Soff
0
Disable................................................... default
1
Enable
Offset 57 – Miscellaneous Control................................... RW
........................................always reads 0
7-1
Reserved
0
Internal THRM# Output on GPO21
0
Disable................................................... default
1
Enable
-86-
Function 4 Regs - Power Management, SMBus and HWM
VT82C686B