TMPM333FDFG Toshiba, TMPM333FDFG Datasheet
TMPM333FDFG
Specifications of TMPM333FDFG
Available stocks
Related parts for TMPM333FDFG
TMPM333FDFG Summary of contents
Page 1
... Bit RISC Microcontroller TX03 Series TMPM333FDFG/FYFG/FWFG ...
Page 2
... TOSHIBA CORPORATION All Rights Reserved ...
Page 3
... ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. ************************************************************************************************************************* TMPM333FDFG/FYFG/FWFG R ...
Page 4
... SFR(register) ・ Each register basically consists of a 32-bit register (some exceptions). ・ The description of each register provides bits, bit symbols, types, initial values after reset and functions. Register name SAMCR TMPM333FDFG/FYFG/FWFG Base Address = 0x0000_0000 Address(Base+) 0x0004 0x000C ...
Page 5
... Register name <Bit Symbol> Exmaple: SAMCR<MODE>="000" or SAMCR<MODE[2:0]>="000" <MODE[2:0]> indicates bit 2 to bit 0 in bit symbol mode (3bit width). ・ Register name [Bit] Example: SAMCR[9:7]="000" It indicates bit 9 to bit 7 of the register SAMCR (32 bit width TDATA Function READ WRITE TMPM333FDFG/FYFG/FWFG MODE ...
Page 6
... TMPM333FDFG/FYFG/FWFG ...
Page 7
Date Revision 2010/6/1 1 2010/10/6 2 Revision History Comment First Release Contents Revised ...
Page 8
...
Page 9
... Table of Contents Introduction: Notes on the description of SFR (Special Function Register) under this specification TMPM333FDFG/FYFG/FWFG 1.1 Features......................................................................................................................................1 1.2 Block Diagram...........................................................................................................................3 1.3 Pin Layout (Top view)...............................................................................................................4 1.4 Pin names and Functions...........................................................................................................5 1.4.1 Sorted by Pin........................................................................................................................................................................5 1.4.2 Sorted by Port....................................................................................................................................................................11 1.5 Pin Numbers and Power Supply Pins......................................................................................16 2 ...
Page 10
... Memory map............................................................................................................................25 4.1.1 Memory map of the TMPM333FDFG...............................................................................................................................26 4.1.2 Memory Map of TMPM333FYFG....................................................................................................................................27 4.1.3 Memory Map of TMPM333FWFG...................................................................................................................................28 4.2 SFR area detail.........................................................................................................................29 5. Reset 5.1 Cold reset.................................................................................................................................31 5.2 Warm reset...............................................................................................................................32 5.2.1 Reset period.......................................................................................................................................................................32 5.2.2 After reset..........................................................................................................................................................................32 6. Clock/Mode control 6.1 Features....................................................................................................................................33 6.2 Registers..................................................................................................................................34 6 ...
Page 11
Exception Request and Detection 7.1.2.2 Exception Handling and Branch to the Interrupt Service Routine (Pre-emption) 7.1.2.3 Executing an ISR 7.1.2.4 Exception exit 7.2 Reset Exceptions......................................................................................................................61 7.3 Non-Maskable Interrupts (NMI)..............................................................................................62 7.4 SysTick....................................................................................................................................62 7.5 Interrupts..................................................................................................................................63 7.5.1 Interrupt Sources................................................................................................................................................................63 7.5.1.1 Interrupt Route ...
Page 12
Port B Register 8.2.2.3 PBDATA (Port B data register) 8.2.2.4 PBCR (Port B output control register) 8.2.2.5 PBFR1 (Port B function register 1) 8.2.2.6 PBPUP (Port B pull-up control register) 8.2.2.7 PBIE (Port B input control register) 8.2.3 Port ...
Page 13
PKCR (Port K output control register) 8.2.11.5 PKFR1(Port K function register 1) 8.2.11.6 PKFR2(Port K function register 2) 8.2.11.7 PKPUP (Port K pull-up control register) 8.2.11.8 PKIE (Port K input control register) 8.3 Block Diagrams of Ports........................................................................................................153 8.3.1 Port ...
Page 14
Up-counter capture register (TBxUC).............................................................................................................................201 9.5.7 Comparators (CP0, CP1).................................................................................................................................................201 9.5.8 Timer Flip-flop (TBxFF0)...............................................................................................................................................201 9.5.9 Capture interrupt (INTCAPx0, INTCAPx1)...................................................................................................................201 9.6 Description of Operations for Each Mode.............................................................................202 9.6.1 16-bit Interval Timer Mode.............................................................................................................................................202 9.6.2 16-bit Event Counter Mode.............................................................................................................................................202 9.6.3 16-bit PPG (Programmable Pulse ...
Page 15
Receive Buffer 10.11.3.2 Receive FIFO Operation 10.11.3.3 I/O interface mode with SCLK output 10.11.3.4 Read Received Data 10.11.3.5 Wake-up Function 10.11.3.6 Overrun Error 10.12 Transmission......................................................................................................................246 10.12.1 Transmission Counter..................................................................................................................................................246 10.12.2 Transmission Control...................................................................................................................................................246 10.12.2.1 I/O Interface Mode 10.12.2.2 UART Mode 10.12.3 ...
Page 16
Arbitration Lost Detection Monitor.............................................................................................................................283 11.5.11 Slave Address Match Detection Monitor.....................................................................................................................285 11.5.12 General-call Detection Monitor...................................................................................................................................285 11.5.13 Last Received Bit Monitor...........................................................................................................................................285 11.5.14 Data Buffer Register (SBIxDBR)................................................................................................................................285 11.5.15 Baud Rate Register (SBIxBR0)...................................................................................................................................285 11.5.16 Software Reset.............................................................................................................................................................285 11.6 Data Transfer Procedure in the I2C ...
Page 17
AD Monitor Function....................................................................................................................................................333 12.4.4 Selecting the Input Channel...........................................................................................................................................334 12.4.5 AD Conversion Details..................................................................................................................................................334 12.4.5.1 Starting AD Conversion 12.4.5.2 AD Conversion 12.4.5.3 Top-priority AD conversion during normal AD conversion 12.4.5.4 Stopping Repeat Conversion Mode 12.4.5.5 Reactivating normal AD conversion 12.4.5.6 Conversion ...
Page 18
Flash Memory Operation 15.1 Flash Memory......................................................................................................................365 15.1.1 Features..........................................................................................................................................................................365 15.1.2 Block Diagram of the Flash Memory Section...............................................................................................................367 15.2 Operation Mode...................................................................................................................368 15.2.1 Reset Operation..............................................................................................................................................................369 15.2.2 User Boot Mode (Single chip mode).............................................................................................................................370 15.2.2.1 (1-A) Method 1: Storing a Programming Routine in the ...
Page 19
... DC Electrical Characteristics (1/3)......................................................................................428 17.3 DC Electrical Characteristics (2/3)......................................................................................429 17.4 DC Electrical Characteristics (3/3)......................................................................................430 17.4.1 TMPM333FDFG/TMPM333FYFG..............................................................................................................................430 17.4.2 TMPM333FWFG...........................................................................................................................................................430 17.5 10-bit ADC Electrical Characteristics.................................................................................431 17.6 AC Electrical Characteristics...............................................................................................432 17.6.1 AC measurement condition...........................................................................................................................................432 17.6.2 Serial Channel (SIO/UART)..........................................................................................................................................432 17.6.2.1 I/O Interface mode 17 ...
Page 20
xii ...
Page 21
... TMPM333FDFG/FYFG/FWFG The TMPM333FDFG/FYFG/FWFG is a 32-bit RISC microprocessor series with an ARM Cortex™-M3 micro- processor core. Product Name TMPM333FDFG TMPM333FYFG TMPM333FWFG Features of the TMPM333FDFG/FYFG/FWFG are as follows: 1.1 Features 1. ARM Cortex-M3 microprocessor core a. Improved code efficiency has been realized through the use of Thumb® -2 instruction. ...
Page 22
... Clock gear function: The high-speed clock can be divided into 1/1, 1/2, 1/4 or 1/8. 14. Endian Little endian 15. Maximum operating frequency: 40 MHz 16. Operating voltage range 2 3.6 V (with on-chip regulator) 17. Temperature range ・ - degrees (except during Flash writing/ erasing) ・ degrees (during Flash writing/ erasing) 18. Package LQFP100-P-1414-0.50H (14mm × 14mm, 0.5mm pitch) TMPM333FDFG/FYFG/FWFG Page 2 ...
Page 23
... Block Diagram Cortex-M3 CPU Debug NVIC CG SIO/UART (3ch) I2C/SIO (3ch) Figure 1-1 TMPM333FDFG/FYFG/FWFGBlock Diagram TMPM333FDFG/FYFG/FWFG I/F FLASH I-Code D-Code I/F RAM System I/F BOOTROM Bus Bridge PORT A~K TMRB (10ch) WDT RTC ADC (12ch) Page 3 ...
Page 24
... Pin Layout (Top view) 1.3 Pin Layout (Top view) Figure 1-2 shows the pin layout of TMPM333FDFG/FYFG/FWFG. RVDD3 XT1 XT2 TB4IN0/PI6 NMI MODE RESET TB4IN1/PI7 TB3IN0/PH6 TB3IN1/PH7 INT2/PJ2 INT3/PJ3 TB6OUT/PJ4 PE3 TEST4 AIN0/PC0 AIN1/PC1 AIN2/PC2 AIN3/PC3 TB5IN0/AIN4/PD0 TB5IN1/AIN5/PD1 TB6IN0/AIN6/PD2 TB6IN1/AIN7/PD3 AIN8/PD4 ...
Page 25
... Pin names and Functions Table 1-1 and Table 1-2 sort the input and output pins of the TMPM333FDFG/FYFG/FWFG by pin or port. Each table includes alternate pin names and functions for multi-function pins. 1.4.1 Sorted by Pin Table 1-1 Pin Names and Functions Sorted by Pin (1/6) ...
Page 26
... I/O port I Inputting the timer B capture trigger I/O I/O port I Inputting the timer B capture trigger I/O I/O port O Sending serial data I/O I/O port I Receiving serial data I/O I/O port I/O Serial clock input/ output I Handshake input pin Page 6 TMPM333FDFG/FYFG/FWFG Function ...
Page 27
... I/O port Timer B output I/O port External interrupt pin I/O port (note) Nch open drain port. I/O port System clock output Alarm output I/O port Timer B output I/O port Timer B output I/O port Debug pin I/O port Debug pin Page 7 TMPM333FDFG/FYFG/FWFG ...
Page 28
... Power supply pin O Connected to a high-speed oscillator. − GND pin I Connected to a high-speed oscillator. − GND pin − Power supply pin I Connected to a low-speed oscillator. O Connected to a low-speed oscillator. I/O I/O port I Inputting the timer B capture trigger Page 8 TMPM333FDFG/FYFG/FWFG Function ...
Page 29
... TEST pin must be left OPEN. Input port Analog input Input port Analog input Input port Analog input Input port Analog input Input port Analog input Inputting the timer B capture trigger Input port Analog input Inputting the timer B capture trigger Page 9 TMPM333FDFG/FYFG/FWFG ...
Page 30
... Function 98 AIN7 TB6IN1 PD4 Function 99 AIN8 PD5 Function 100 AIN9 Input/ Output I Input port I Analog input I Inputting the timer B capture trigger I Input port I Analog input I Inputting the timer B capture trigger I Input port I Analog input I Input port I Analog input Page 10 TMPM333FDFG/FYFG/FWFG Function ...
Page 31
... I/O port I/O I/O port I/O I/O port I/O I/O port I/O I/O port I Input port I Analog input I Input port I Analog input I Input port I Analog input I Input port I Analog input I Input port I Analog input I Inputting the timer B capture trigger Page 11 TMPM333FDFG/FYFG/FWFG ...
Page 32
... CTS1 I Handshake input pin PF0 I/O I/O port TXD2 O Sending serial data PF1 I/O I/O port RXD2 I Receiving serial data PF2 I/O I/O port SCLK2 I/O Serial clock input/ output CTS2 I Handshake input pin PF3 I/O I/O port Page 12 TMPM333FDFG/FYFG/FWFG Function ...
Page 33
... Setting a single boot mode: This pin goes into single boot mode by sampling "Low" at the rise of a RESET signal. I/O I/O port I Inputting the timer B capture trigger I/O I/O port I Inputting the timer B capture trigger I/O I/O port I Inputting the timer B capture trigger Page 13 TMPM333FDFG/FYFG/FWFG ...
Page 34
... I/O I/O port TB6OUT O Timer B output PJ5 I/O I/O port TB7OUT O Timer B output PJ6 I/O I/O port INT6 I External interrupt pin PJ7 I/O I/O port INT7 I External interrupt pin I/O port PK0 I/O (note) Nch open drain port. Page 14 TMPM333FDFG/FYFG/FWFG Function ...
Page 35
... AVDD must be connected to power supply even if A/D converter is not used. − GND pin − Power supply pin − Power supply pin − GND pin − Power supply pin − GND pin − GND pin − Power supply pin Page 15 TMPM333FDFG/FYFG/FWFG ...
Page 36
... Pin Numbers and Power Supply Pins 1.5 Pin Numbers and Power Supply Pins Table 1-3 Pin Numbers and Power Supplies Power supply DVDD3 AVDD3 RVDD3 Voltage range Pin No. PA,PB,PE,PF,PG,PH,PI,PJ,PK,X1,X2,XT1, 14, 62,71 XT2,RESET,NMI,MODE 2 Page 16 TMPM333FDFG/FYFG/FWFG Pin name PC,PD − ...
Page 37
... Number of Interrupt Inputs The number of interrupt inputs can optionally be defined from 1 to 240 in the Cortex-M3 core. TMPM333FDFG/FYFG/FWFG has 46 interrupt inputs. The number of interrupt inputs is reflected in <IN- TLINESNUM[4:0]> bit of NVIC register. In this product, if read <INTLINESNUM[4:0]> bit, "0y00001" is read out. Product Name ...
Page 38
... SysTick The Cortex-M3 core has a SysTick timer which can generate SysTick exception. In the TMPM333FDFG/FYFG/FWFG, the clock that is input from X1 pin dividing used as a count clock for the Systic timer. SysTick calibration register can set a calibration value to measure 10ms. In this product, when 8MHz is input to X1 pin, calibration value is set to 0x9C4 which can measure 10ms. Additionally, if this value is read as " ...
Page 39
... The Cortex-M3 core has event output signals and event input signals. An event output signal is output by SEV instruction execution event is input, the core returns from low-power consumption mode caused by WFE in- struction. TMPM333FDFG/FYFG/FWFG does not use event output signals and event input signals. Please do not use SEV instruction and WFE instruction. 2.5 Power Management The Cortex-M3 core provides power management system which uses SLEEPING signals and SLEEPDEEP signals ...
Page 40
... Exclusive access TMPM333FDFG/FYFG/FWFG Page 20 ...
Page 41
... Specification Overview TMPM333FDFG/FYFG/FWFG contains the Serial Wire JTAG Debug Port (SWJ-DP) unit for interfacing with the debugging tools and the Embedded Trace Macrocell™(ETM) unit for instruction trace output.Trace data is output to the dedicated pins(TRACEDATA[3:0], SWV) for the debugging via the on-chip Trace Port Interface Unit (TPIU). ...
Page 42
... Input JTAG Test RESET Output TRACE Clock Output Output TRACE DATA Output0 Output TRACE DATA Output1 Output TRACE DATA Output2 Output TRACE DATA Output3 Page 22 TMPM333FDFG/FYFG/FWFG SW Debug Function Explanation Serial Wire Data Input/Output Input Serial Wire Clock (Serial Wire Viewer Output ...
Page 43
... Reset Vector Break TMPM333FDFG/FYFG/FWFG is prohibited from transmission with debug tools while reset caused by RESET pin is effective.When setting a stop by using reset vector, set the following procedure after reset; set break points from the debug tools, then set the application interrupt and the <SYSRESETREQ> bit of the reset control register to reset again. Note:Do not reset with < ...
Page 44
... Important points of using debug interface pins used as general-purpose ports TMPM333FDFG/FYFG/FWFG is prohibited from transmission with debug tools while reset caused by RE- SET pin is effective. Therefor it cannot change to the debug mode. The PA0, PA1, PB0, PB1 and PB2 ports are the debug interface pins after reset however if these pins are changed to the general-purpose port immediately after reset, the control from the debug tools are not accepted under some circumstances ...
Page 45
... Memory Map 4.1 Memory map The memory maps for theTMPM333FDFG/FYFG/FWFG are based on the ARM Cortex-M3 processor core mem- ory map. The internal ROM is mapped to the code of the Cortex-M3 core memory, the internal RAM is mapped to the SRAM region and the special function register (SFR) is mapped to the peripheral region respectively. ...
Page 46
... Memory map 4.1.1 Memory map of the TMPM333FDFG Figure 4-1shows the memory map of the TMPM333FDFG. Vendor-Specific CPU Register Region Fault SFR Fault Internal RAM (32K) Fault Internal ROM (512K) Figure 4-1 Memory Map (TMPM333FDFG) Page 26 TMPM333FDFG/FYFG/FWFG ...
Page 47
... Note:In addition to 256KB flash area, the TMPM333FYFG provides 128-word data/ password area (1 page) for Show Product Information command in the address range 0x0007_FE00 - 0x0007_FFFF. See the Chapter "Flash Memory Operation" for details on the single boot mode. Do not Access to the range from 0x0004_0000 through the password area. TMPM333FDFG/FYFG/FWFG Vendor-Specific CPU Register Region Fault ...
Page 48
... Memory map 4.1.3 Memory Map of TMPM333FWFG Figure 4-3 shows the memory map of the TMPM333FWFG. Vencor-Specific CPU Register Region Fault SFR Fault Internal RAM (8K) Fault Internal ROM (128K) Figure 4-3 Memory Map (TMPM333FWFG) Page 28 TMPM333FDFG/FYFG/FWFG ...
Page 49
... TMPM333FDFG/FYFG/FWFG Peripheral Reserved 0x4000_0190 to 0x4000_0193 0x4000_01D0 to 0x4000_01D3 PORT 0x4000_0210 to 0x4000_0213 0x4000_0250 to 0x4000_0253 TMRB(10ch) I2C/SIO(3ch) SIO/UART(3ch) ADC(12ch) 0x4003_0024 to 0x4003_002F ...
Page 50
... SFR area detail TMPM333FDFG/FYFG/FWFG Page 30 ...
Page 51
... Reset The TMPM333FDFG/FYFG/FWFG has three reset sources: an external reset pin (RESET), a watchdog timer (WDT) and the setting <SYSRESETREQ> in the Application Interrupt and Reset Control Register. For reset from the WDT, refer to the chapter on the WDT. For reset from <SYSRESETREQ>, refer to "Cortex-M3 Technical Reference Manual". ...
Page 52
... Reset period As a precondition, ensure that the power supply voltage is within the operating range and the internal high- frequency oscillator is providing stable oscillation. To reset the TMPM333FDFG/FYFG/FWFG, assert the RESET signal (active low) for a minimum duration of 12 system clocks. 5.2.2 After reset A warm reset initializes the majority of the Cortex-M3 processor core's system control registers and internal function registers ...
Page 53
... Controls the system clock ・ Controls the prescaler clock ・ Controls the PLL multiplication circuit ・ Controls the warm-up timer In addition to NORMAL mode, the TMPM333FDFG/FYFG/FWFG can operate in three types of low power mode to reduce power consumption according to its usage conditions. TMPM333FDFG/FYFG/FWFG Page 33 ...
Page 54
... The following table shows the CG-related registers and addresses. System control register Oscillation control register Standby control register PLL selection register System clock selection register Register name CGSYSCR CGOSCCR CGSTBYCR CGPLLSEL CGCKSEL Page 34 TMPM333FDFG/FYFG/FWFG Base Address = 0x4004_0200 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 ...
Page 55
... Reserved Specifies the prescaler clock to peripheral I/O. 7-3 − R Read as 0. 2-0 GEAR[2:0] R/W High-speed clock gear (fc) gear 000: fc 001: Reserved 010: Reserved 011: Reserved 100: fc/2 101: fc/4 110: fc/8 111: Reserved FPSEL - Function Page 35 TMPM333FDFG/FYFG/FWFG SCOSEL PRCK GEAR ...
Page 56
... Stop 1: Oscillation Specifies operation of the PLL. It stops after reset.Setting the bit is required. Status of Warm-up timer (WUP) 0:Warm-up completed 1: Warm-up operation Enables to monitor the status of the warm-up timer. Operation of warm-up timer 0: don't care 1: starting warm-up Enables to start the warm-up timer. Page 36 TMPM333FDFG/FYFG/FWFG ...
Page 57
... High-speed oscillator operation after releasing the STOP mode. 0: Stop 1:Oscillation 7-3 − R Read as 0. 2-0 STBY[2:0] R/W Low power consumption mode 000: Reserved 001: STOP 010: SLEEP 011: IDLE 100: Reserved 101: Reserved 110: Reserved 111: Reserved Function Page 37 TMPM333FDFG/FYFG/FWFG DRVE RXTEN RXEN STBY ...
Page 58
... After reset 0 Bit Bit Symbol Type 31-1 − PLLSEL R Read as 0. Use of PLL 0: Disuse. X1 selected 1: Use Specifies use or disuse of the clock multiplied by the PLL. "X1" is automatically set after reset. Resetting is required when using the PLL. Page 38 TMPM333FDFG/FYFG/FWFG PLLSEL Function ...
Page 59
... SYSCKFLG R System clock status 0: High-speed (fc) 1: Low-speed (fs) Shows the status of the system clock. Switching the oscillator with <SYSCK> generates time lag to complete. If the output of the oscillator specified in <SYSCK> is read out by <SYSCLKFLG>, the switching has been completed Function Page 39 TMPM333FDFG/FYFG/FWFG SYSCK SYSCKFLG ...
Page 60
... Clock quadrupled by PLL : Clock specified by CGPLLSEL<PLLSEL> (high-speed clock) : Clock specified by CGSYSCR<GEAR[2:0]> : Clock specified by CGCKSEL<SYSCK> (system clock) : Clock specified by CGSYSCR<FPSEL> : Clock specified by CGSYSCR<PRCK[2:0]> (prescaler clock) : fc, fc/2, fc/4, fc/8 : fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16, fperiph/32 : fsys : fosc/32 : oscillating : oscillating : stop : fc (no frequency dividing) Page 40 TMPM333FDFG/FYFG/FWFG ...
Page 61
... PLL <GEAR[2:0]> fpll = fosc 4 T0 CGSYSCR 1/16 1/32 <PRCK[2:0]> 1/2 CGSYSCR <SCOSEL[1:0]> Page 41 TMPM333FDFG/FYFG/FWFG ADC conversion clock <ADCLK> CGSYSCR<FPSEL> fperiph (TO peripheal I/O) fgear fsys CGCKSEL <SYSCK> fs Systick Timer input CPU(STCLK) PeripheralI/O prescaler input TMRB, SIO 【AHB-Bus I/O】 CPU(HCLK/FCLK), ROM, RAM, BOOT ROM 【 ...
Page 62
... Page 42 TMPM333FDFG/FYFG/FWFG Low-speed clock (fs) CGOSCCR<WUPSEL> = "1" − With WUP 1.953 (ms) 3.906 (ms) 7.813 (ms) /input frequency 1.0 (s) /input frequency 2.0 (s) /input frequency 4.0 (s) /input frequency 8.0 (s) ...
Page 63
... Switch the system clock to high speed (fgear) CGCKSEL<SYSCKFLG> Read : Confirm that the current state is "0" (the current system clock is fgear) CGOSCCR<XTEN> = "0" : Disable the low-speed oscillation (fs) Note:When switching the system clock, ensure that the switching has been completed by reading the CGSYSCR<SYSCKFLG>. TMPM333FDFG/FYFG/FWFG Page 43 ...
Page 64
... Clock control 6.3.6 System Clock The TMPM333FDFG/FYFG/FWFG offers two selectable system clocks: low-speed or high-speed. The high- speed clock is dividable. Note 1: Switching of clock gear is executed when a value is written to the CGSYSCR<GEAR[2:0]> register. The actual switching takes place after a slight delay. 6.3.6.1 High speed clock ・ ...
Page 65
... Note:The phase difference (AC timing) between the system clock output by the SCOUT and the internal clock is not guaranteed. Low power consumption mode SLOW IDLE Output the fs clock Output the fsys/2 clock Output the fsys clock Fixed to "0" or "1". clock Page 45 TMPM333FDFG/FYFG/FWFG SLEEP STOP ...
Page 66
... When the low-speed clock is not used, the SLOW and SLEEP modes cannot be used. Figure 6-2 shows a mode transition diagram. For a detail of sleep-on-exit, refer to "Cortex-M3 Technical Reference Manual." IDLE SLEEP mode NORMAL mode / sleep on exit / sleep on exit SLOW mode / sleep on exit Figure 6-2 Mode Transition Diagram Page 46 TMPM333FDFG/FYFG/FWFG / sleep on exit STOP / sleep on exit ...
Page 67
... Note 1: Be sure to stop peripheral functions except for the CPU, RTC and I/O ports before switching to the SLOW mode. Note 2: In the slow mode, be sure not to perform reset using the Application Interrupt and Reset Control Register <SYSRESETREQ> of the Cortex-M3 NVIC register. TMPM333FDFG/FYFG/FWFG Page 47 ...
Page 68
... By releasing the SLEEP mode, the device returns to the preceding mode of the SLEEP mode and starts oper- ation. Note:When PA1 (pin number 56) is configured as a debug function pin, it prevents the low power con- sumption mode from being fully effective. Configure PA1 to function as a general-purpose port if the debug function is not used. TMPM333FDFG/FYFG/FWFG Page 48 ...
Page 69
... Enabled when data is valid. Output Disabled when data is invalid. Input ο Output × Input × Output × CGSTBYCR Mode <STBY[2:0]> STOP 001 SLEEP 010 IDLE 011 Page 49 TMPM333FDFG/FYFG/FWFG <DRVE> × "High" level output. ο Depends on (PxIE[m]) ο Depends on (PxCR[m]) Depends on (PxIE[m]) Depends on (PxCR[m]) ...
Page 70
... Page 50 TMPM333FDFG/FYFG/FWFG SLEEP STOP × × ο * (Note 3) × × × × × × × × × × ο × ο ...
Page 71
... NORMAL mode and all the registers are initialized as is the case with normal reset. Note that returning to the STOP mode by reset does not induce the automatic warm-up. Keep the reset signal valid until the oscillator operation becomes stable. Refer to "Interrupts" for details. TMPM333FDFG/FYFG/FWFG IDLE SLEEP ο ο ...
Page 72
... Not required IDLE → NORMAL Not required SLEEP → NORMAL Auto-warm-up SLEEP → SLOW Not required SLOW → NORMAL (Note 2) SLOW → SLEEP Not required SLOW → STOP Not required STOP → NORMAL Auto-warm-up (Note 3) STOP → SLOW Auto-warm-up Page 52 TMPM333FDFG/FYFG/FWFG ...
Page 73
... NORMAL Mode fosc Warm-up fsys (System clock) fs (Low speed clock) System clock stops TMPM333FDFG/FYFG/FWFG Release event occurs. STOP High-speed clock starts oscillating. Warm-up completes. Warm-up starts. System clock starts Release event occurs. SLEEP Oscillation continues. High-speed clock starts oscillating. ...
Page 74
... WFI insutruction/ Release eventoccurs. sleep on exit STOP System clock stops Low-speed clock starts oscillating. Warm-up starts. WFI instruction / sleep on exit SLEEP System clock stops. Page 54 TMPM333FDFG/FYFG/FWFG SLOW Warm-up completes. System clock starts. Release event occurs. SLOW System clock starts. ...
Page 75
... For detailed descriptions on each exception, refer to "Cortex-M3 Technical Reference Manual". ・ Reset ・ Non-Maskable Interrupt (NMI) ・ Hard Fault ・ Memory Management ・ Bus Fault ・ Usage Fault ・ SVCall (Supervisor Call) ・ Debug Monitor ・ PendSV ・ SysTick ・ External Interrupt TMPM333FDFG/FYFG/FWFG Page 55 ...
Page 76
... The CG/CPU detects the exception request. The CPU handles the exception request. The CPU branches to the corresponding interrupt service routine (ISR). Necessary processing is executed. The CPU branches to another ISR or returns to the previous program. Page 56 TMPM333FDFG/FYFG/FWFG Indicates software handling. See Section 7.1.2.1 Section 7.1.2.2 Section 7.1.2.3 ...
Page 77
... A priority is compared with the pre-emption priority. If the priority is the same as the pre- emption priority, then it is compared with the sub priority. If the sub priority is the same as the priority, the smaller the exception number, the higher the priority. TMPM333FDFG/FYFG/FWFG Description Reset pin, WDT or SYSRETREQ ...
Page 78
... Pre-emption Subpriority field field [7:1] [0] [7:2] [1:0] [7:3] [2:0] [7:4] [3:0] [7:5] [4:0] [7:6] [5:0] [7] [6:0] None [7:0] the case of 3-bit configuration, the priority is set as <PRI_n[7:5]> and <PRI_n[4:0]> is "00000". Page 58 TMPM333FDFG/FYFG/FWFG Number of Number of pre-emption subpriorities priorities 128 128 1 256 ...
Page 79
... Bus Fault 0x18 Usage Fault 0x1C ~ 0x28 Reserved 0x2C SVCall 0x30 Debug Monitor 0x34 Reserved 0x38 PendSV 0x3C SysTick 0x40 External Interrupt TMPM333FDFG/FYFG/FWFG <previous> xPSR PC LR r12 Contents Setting Initial value of the main stack Required ISR address Required ISR address Required ...
Page 80
... Pops the eight registers (PC, xPSR r3, r12 and LR) from the stack and adjust the SP. Loads the current active interrupt number from the stacked xPSR. The CPU uses this to track which interrupt to return to. If returning to an exception (Handler Mode SP_main. If returning to Thread Mode, SP can be SP_main or SP_process. Page 60 TMPM333FDFG/FYFG/FWFG ...
Page 81
... The watchdog timer (WDT) has a reset generating feature. For details, see the chapter on the WDT. ・ Reset exception by SYSRESETREQ A reset can be generated by setting the SYSRESETREQ bit in the NVIC's Application Interrupt and Reset Control Register. Note:Do not reset with <SYSRESETREQ> in SLOW mode. TMPM333FDFG/FYFG/FWFG Page 61 ...
Page 82
... SysTick Calibration Value Register also varies with each product. Note:In this product, the system timer counts based on a clock obtained by dividing the clock input from the X1 pin by 32.The SysTick Calibration Value Register is set to 0x9C4, which provides 10 ms timing when the clock input from MHz. TMPM333FDFG/FYFG/FWFG Page 62 ...
Page 83
... If interrupts from the external interrupt pins are not used to release standby, they are directly input to the CPU, not through the logic for standby release (route 6). Peripheral function External Port interrupt pin Peripheral function Interruptrequest <INTxEN> Exiting standby mode Clock generator Figure 7-1 Interrupt Route Page 63 TMPM333FDFG/FYFG/FWFG CPU ...
Page 84
... Set the port control register so that the external pin can perform as an interrupt function pin. Set the peripheral function to make it possible to output interrupt requests. See the chapter of each peripheral function for details. An interrupt request can be generated by setting the relevant bit of the Interrupt Set-Pending Page 64 TMPM333FDFG/FYFG/FWFG ...
Page 85
... INT6 Interrupt pin (PJ6/39pin) 35 INT7 Interrupt pin (PJ7/58pin) 36 INTRX2 Serial reception (channel.2) 37 INTTX2 Serial transmission (channel.2) 38 INTSBI2 Serial bus interface 2 39 Reserved - TMPM333FDFG/FYFG/FWFG active level (Clearing standby) Selectable Falling edge Selectable Page 65 CG interrupt mode control register CGIMCGA CGIMCGB CGIMCGC CGIMCGC ...
Page 86
... TMRB match detection 9 16-bit TMRB input capture 20 16-bit TMRB input capture 21 16-bit TMRB input capture 30 16-bit TMRB input capture 31 16-bit TMRB input capture 40 16-bit TMRB input capture 41 A/D conversion completion Page 66 TMPM333FDFG/FYFG/FWFG active level CG interrupt mode (Clearing standby) control register ...
Page 87
... If multiple interrupt requests occur simultaneously, the interrupt request with the highest priority is detected according to the priority order. The CPU handles the interrupt. CPU handles interrupt The CPU pushes register contents to the stack before entering the ISR. TMPM333FDFG/FYFG/FWFG indicates hardware handling. Details Page 67 indicates software See " ...
Page 88
... You can assign a priority level by writing to <PRI_n> field in an Interrupt Priority Register of the NVIC register. Details Program for the ISR. Clear the interrupt source if needed. Configure to return to the preceding program of the ISR. ← "1" (interrupt disabled) Page 68 TMPM333FDFG/FYFG/FWFG See "7.5.2.6 Interrupt Service Routine (ISR)" ...
Page 89
... Note:m: corresponding bit (6) Configuring the clock generator For an interrupt source to be used for exiting a standby mode, you need to set the active level and enable interrupts in the CGIMCG register of the clock generator. The CGIMCG register is capable of configuring each source. TMPM333FDFG/FYFG/FWFG Page 69 ...
Page 90
... Be sure to clear each interrupt request in the ISR. ← active level ← Value corresponding to the interrupt to be used ← "1" (interrupt enabled) ← "1" ← "1" ← "0" Page 70 TMPM333FDFG/FYFG/FWFG ...
Page 91
... Therefore, the interrupt source must be cleared. Clearing the interrupt source automatically clears the interrupt request signal from the clock generator interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding value in the CGICRCG register. When an active edge occurs again, a new interrupt request will be detected. TMPM333FDFG/FYFG/FWFG Page 71 ...
Page 92
... Reserved Reserved Reserved Note:Access to the "Reserved" areas is prohibited. Register name Register name CGICRCG CGNMIFLG CGRSTFLG CGIMCGA CGIMCGB CGIMCGC - - - - - Page 72 TMPM333FDFG/FYFG/FWFG Base Address = 0xE000_E000 Address 0x0010 0x0014 0x0018 0x001C 0x0100 0x0104 0x0180 0x0184 0x0200 0x0204 0x0280 0x0284 0x0400 ~ 0x0430 0x0D08 0x0D0C 0x0D18, 0x0D1C, 0x0D20 ...
Page 93
... Clears on read of any part of the SysTick Control and Status Register. 15-3 − R Read CLKSOURCE R/W 0: External reference clock 1: CPU clock 1 TICKINT R not pend SysTick 1: Pend SysTick 0 ENABLE R/W 0: Disable 1: Enable If "1" is set, it reloads with the value of the Reload Value Register and starts operation CLKSOURCE Function Page 73 TMPM333FDFG/FYFG/FWFG COUNTFLAG TICKINT ENABLE ...
Page 94
... Note:In this product, the system timer counts based on a clock obtained by dividing the clock input from the X1 pin by 32 RELOAD Undefined RELOAD Undefined RELOAD Undefined Read as 0. Reload value Set the value to load into the SysTick Current Value Register when the timer reaches "0". Page 74 TMPM333FDFG/FYFG/FWFG Function ...
Page 95
... Read as 0. 23-0 CURRENT R/W [Read] Current SysTick timer value [Write] Clear Writing to this register with any value clears Clearing this register also clears the <COUNTFLAG> bit of the SysTick Control and Status Register CURRENT Undefined CURRENT Undefined CURRENT Undefined Function Page 75 TMPM333FDFG/FYFG/FWFG ...
Page 96
... X1 pin by 32.The SysTick Calibration Value Register is set to a value that provides 10 ms timing when the cock input from MHz SKEW - - TENMS TENMS TENMS Reference clock provided 1: No reference clock 0: Calibration value is 10 ms. 1: Calibration value is not 10 ms. Read as 0. Calibration value Reload value to use for 10 ms timing (0x9C4). (Note) Page 76 TMPM333FDFG/FYFG/FWFG Function ...
Page 97
... SETENA SETENA SETENA (Interrupt 20) (Interrupt 19) (Interrupt 18 SETENA - - (Interrupt 11) (Interrupt 10 SETENA SETENA SETENA (Interrupt 4) (Interrupt 3) (Interrupt Function Page 77 TMPM333FDFG/FYFG/FWFG SETENA SETENA SETENA (Interrupt 25) (Interrupt 24 SETENA SETENA SETENA (Interrupt 17) (Interrupt 16 SETENA SETENA SETENA (Interrupt 9) (Interrupt SETENA SETENA SETENA (Interrupt 1) (Interrupt 0) 0 ...
Page 98
... Interrupt number [38:32] [Write] 1: Enable [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. Writing "1" bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Page 78 TMPM333FDFG/FYFG/FWFG ...
Page 99
... CLRENA CLRENA CLRENA (Interrupt 20) (Interrupt 19) (Interrupt 18 CLRENA - - (Interrupt 11) (Interrupt 10 CLRENA CLRENA CLRENA (Interrupt 4) (Interrupt 3) (Interrupt Function Page 79 TMPM333FDFG/FYFG/FWFG CLRENA CLRENA CLRENA (Interrupt 25) (Interrupt 24 CLRENA CLRENA CLRENA (Interrupt 17) (Interrupt 16 CLRENA CLRENA CLRENA (Interrupt 9) (Interrupt CLRENA CLRENA CLRENA (Interrupt 1) (Interrupt 0) 0 ...
Page 100
... Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Page 80 TMPM333FDFG/FYFG/FWFG ...
Page 101
... Undefined Undefined Undefined SETPEND - - (Interrupt 11) (Interrupt 10) Undefined Undefined Undefined SETPEND SETPEND (Interrupt 4) (Interrupt 3) (Interrupt 2) Undefined Undefined Undefined Function Page 81 TMPM333FDFG/FYFG/FWFG SETPEND SETPEND SETPEND (Interrupt 25) (Interrupt 24) Undefined Undefined Undefined SETPEND SETPEND SETPEND (Interrupt 17) (Interrupt 16) Undefined Undefined Undefined SETPEND SETPEND SETPEND ...
Page 102
... Writing "1" bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Clear and Interrupt Set-Pending Register bit by writing "1" to the corresponding bit in the Interrupt Clear-Pending Register. Page 82 TMPM333FDFG/FYFG/FWFG ...
Page 103
... Undefined Undefined Undefined CLRPEND CLRPEND - - (Interrupt 11) (Interrupt 10) Undefined Undefined Undefined CLRPEND CLRPEND CLRPEND (Interrupt 4) (Interrupt 3) (Interrupt 2) Undefined Undefined Undefined Function Page 83 TMPM333FDFG/FYFG/FWFG CLRPEND CLRPEND (Interrupt 25) (Interrupt 24) Undefined Undefined Undefined CLRPEND CLRPEND (Interrupt 17) (Interrupt 16) Undefined Undefined Undefined CLRPEND CLRPEND (Interrupt 9) (Interrupt 8) Undefined ...
Page 104
... Writing "1" bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Page 84 TMPM333FDFG/FYFG/FWFG ...
Page 105
... PRI_1 PRI_6 PRI_5 PRI_10 PRI_9 − − PRI_18 PRI_17 PRI_22 PRI_21 PRI_26 PRI_25 PRI_30 PRI_29 PRI_34 PRI_33 PRI_38 PRI_37 PRI_42 PRI_41 PRI_46 PRI_45 − PRI_49 Function Page 85 TMPM333FDFG/FYFG/FWFG PRI_0 PRI_4 PRI_8 − PRI_16 PRI_20 PRI_24 PRI_28 PRI_32 PRI_36 PRI_40 PRI_44 PRI_48 ...
Page 106
... The offset must be aligned based on the number of exceptions in the table.This means that the minimum alignment is 32 words that you can use for interrupts.For more interrupts, you must adjust the alignment by rounding up to the next power of two. Read as 0. Page 86 TMPM333FDFG/FYFG/FWFG TBLOFF ...
Page 107
... Resets the system, with the exception of debug components (FPB, DWT and ITM) by setting "1" and this bit is also zero cleared. Note 1: Little-endian is the default memory format for this product. Note 2: When SYSRESETREQ is output, warm reset is performed on this product. <SYSRESETREQ> is cleared by warm reset VECTKEY/VECTKEYSTAT VECTKEY/VECTKEYSTAT SYSRESET - - - REQ Function Page 87 TMPM333FDFG/FYFG/FWFG PRIGROUP VECTCLR VECTRESET ACTIVE ...
Page 108
... PRI_15 PRI_14 (SysTick) (PendSV PRI_7 - PRI_6 - PRI_5 - PRI_4 - Reserved Read as 0. Priority of Usage Fault Read as 0. Priority of Bus Fault Read as 0. Priority of Memory Management Read as 0. Page 88 TMPM333FDFG/FYFG/FWFG PRI_5 PRI_4 (Bus Fault) (Memory Management) PRI_9 PRI_8 PRI_13 PRI_12 (Debug Monitor ...
Page 109
... PendSV 0: Inactive 1: Active 9 − R Read MONITORACT R/W Debug Monitor 0: Inactive 1: Active 7 SVCALLACT R/W SVCall 0: Inactive 1: Active 6-4 − R Read USGFAULT - - - USGFAULT SYSTICKACT PENDSVACT PENDED PENDED USGFAULT - - ACT Function Page 89 TMPM333FDFG/FYFG/FWFG BUSFAULT MEMFAULT ENA ENA ENA MONITOR - ACT BUSFAULT MEMFAULT - ACT ACT ...
Page 110
... MEMFAULT R/W ACT Note:You must clear or set the active bits with extreme caution because clearing and setting these bits does not repair stack contents. Usage Fault 0: Inactive 1: Active Read as 0. Bus Fault 0: Inactive 1: Active Memory Management 0: Inactive 1: Active Page 90 TMPM333FDFG/FYFG/FWFG Function ...
Page 111
... INT2 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edges 17 − R Reads as undefined. 16 INT2EN R/W INT2 clear input 0:Disable 1: Enable 15 − R Read EMCG3 EMST3 EMCG2 EMST2 EMCG1 EMST1 EMCG0 EMST0 Function Page 91 TMPM333FDFG/FYFG/FWFG INT3EN 0 Undefined INT2EN 0 Undefined INT1EN 0 Undefined INT0EN 0 Undefined 0 ...
Page 112
... INT0 standby clear request. (101~111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edges active level of INT0 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edges Reads as undefined. INT0 clear input 0:Disable 1: Enable Page 92 TMPM333FDFG/FYFG/FWFG Function ...
Page 113
... Falling edge 011: Rising edge 100: Both edges 3-2 EMST4[1:0] R active level of INT4 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edges 1 − R Reads as undefined EMCG5 EMST5 EMCG4 EMST4 Function Page 93 TMPM333FDFG/FYFG/FWFG Undefined Undefined INT5EN 0 Undefined INT4EN 0 Undefined 0 ...
Page 114
... If interrupts are cleared with the CGICRCG register, <EMSTx> is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited. INT4 clear input 0:Disable 1: Enable Page 94 TMPM333FDFG/FYFG/FWFG Function ...
Page 115
... INT6 standby clear request. 00: − 01: Rising edge 10: Falling edge 11: Both edges 9 − R Reads as undefined. 8 INT9EN R/W INT6 clear input 0:Disable 1: Enable 7 − R Read EMCGA EMSTA EMCG9 EMST9 EMCG8 EMST8 Function Page 95 TMPM333FDFG/FYFG/FWFG Undefined INTAEN 0 Undefined INT9EN 0 Undefined INT8EN 0 Undefined 0 ...
Page 116
... Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited. active level setting of INTRTC standby clear request. Set it as shown below. 010: Falling edge active level of INTRTC standby clear request. 00: − 01: Rising edge 10: Falling edge 11: Both edges Reads as undefined. INTRTC clear input 0:Disable 1: Enable Page 96 TMPM333FDFG/FYFG/FWFG Function ...
Page 117
... Type 31-5 − R Read as 0. 4-0 ICRCG[4:0] W Clear interrupt requests. 0_0000: INT0 0_0001: INT1 0_0010: INT2 0_0011: INT3 0_0100: INT4 0_0101: INT5 0_0110: Reserved 0_0111: Reserved 0_1000: INTRTC 0_1001: INT6 0_1010: INT7 0_1011 to 1_1111: setting prohibited. Read ICRCG Function Page 97 TMPM333FDFG/FYFG/FWFG ...
Page 118
... Type 31-2 − NMIFLG1 R 0 NMIFLG0 R Note:<NMIFLG> are cleared to "0" when they are read Read as 0. NMI source generation flag 0: not applicable 1: generated from NMI pin NMI source generation flag 0: not applicable 1: generated from WDT Page 98 TMPM333FDFG/FYFG/FWFG NMIFLG1 NMIFLG0 Function ...
Page 119
... Note 1: This flag indicates a reset generated by the SYSRESETREQ bit of the Application Interrupt and Reset Control Register of the CPU's NVIC. Note 2: This register is not cleared automatically. Write "0" to clear the register SYSRSTF - WDTRSTF Function Page 99 TMPM333FDFG/FYFG/FWFG PINRSTF PONRSTF ...
Page 120
... Exception/Interrupt-Related Registers TMPM333FDFG/FYFG/FWFG Page 100 ...
Page 121
... Port Functions 8.1.1 Function Lists TMPM333FDFG/FYFG/FWFG has 78 ports. Besides the ports function, these ports can be used as I/O pins for peripheral functions. Table 8-1, Table 8-2 and Table 8-3 show the port function table. Table 8-1 Port Function List (Port A-Port C) ...
Page 122
... I/O Pull-up ο − I/O Pull-up ο − I/O Pull-up ο − I/O Pull-up − − Page 102 TMPM333FDFG/FYFG/FWFG Program- Function pin mable Open-drain − AIN4, TB5IN0 − AIN5, TB5IN1 − AIN6, TB6IN0 − AIN7, TB6IN1 − AIN8 − AIN9 − ...
Page 123
... Port K PK1 I/O Pull-up PK2 I/O Pull-up ο : Exist - : Not exist Note 1: N-ch open drain port. Note 2: The noise elimination width of the noise filter is approximately 30 ns under typical conditions. TMPM333FDFG/FYFG/FWFG Program- Schmitt Noise mable Function pin input Filter Open-drain ο − ...
Page 124
... When PxOD is set "1",output buffer is disabled and pseudo-open-drain is materialized. ・ PxPUP: Port x pull-up control register To control program pull ups. ・ PxPDN: Port x pull-down control register To control programmable pull downs. ・ PxIE: Port x input control register To control inputs. For avoided through current, default setting prohibits inputs. TMPM333FDFG/FYFG/FWFG Page 104 ...
Page 125
... Precautions for Mode Transition between STOP and SLEEP If PA1 is configured as a debug function pin of TCK/SWCLK, it prevents the low power consumption mode from being fully effective. Configure PA1 to function as a general-purpose port if the debug function is not used. TMPM333FDFG/FYFG/FWFG I/O <DRVE> Input only × ...
Page 126
... Port A output control register Port A function register 1 Port A pull-up control register Port A pull-down control register Port A input control register Register name PADATA PACR PAFR1 PAPUP PAPDN PAIE Page 106 TMPM333FDFG/FYFG/FWFG Base Address = 0x4000_0000 Address (Base+) 0x0000 0x0004 0x0008 0x002C 0x0030 0x0038 0 T12 ...
Page 127
... After reset bit symbol PA7C PA6C After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PA7C-PA0C R/W Output 0: disable 1: enable PA5 PA4 PA3 Function PA5C PA4C PA3C Function Page 107 TMPM333FDFG/FYFG/FWFG PA2 PA1 PA0 PA2C PA1C PA0C ...
Page 128
... R 6 PA6F1 R/W 5 PA5F1 R/W 4 PA4F1 R/W 3 PA3F1 R/W 2 PA2F1 R/W 1 PA1F1 R/W 0 PA0F1 R PA6F1 PA5F1 PA4F1 Read PORT 1: TRACEDATA3 0: PORT 1: TRACEDATA2 0: PORT 1: TRACEDATA1 0: PORT 1: TRACEDATA0 0: PORT 1: TRACECLK 0: PORT 1: TCK/SWCLK 0: PORT 1: TMS/SWDIO Page 108 TMPM333FDFG/FYFG/FWFG PA3F1 PA2F1 PA1F1 Function PA0F1 1 ...
Page 129
... After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-2 − R Read PA1DN R/W Pull-down 0: Disable 1: Enable 0 − R Read PA5UP PA4UP PA3UP Function Function Page 109 TMPM333FDFG/FYFG/FWFG PA2UP - PA0UP PA1DN - ...
Page 130
... After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol PA7IE After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PA7IE-PA0IE R PA6IE PA5IE PA4IE Read as 0. Input 0: DIsable 1: Enable Page 110 TMPM333FDFG/FYFG/FWFG PA3IE PA2IE PA1IE Function PA0IE 1 ...
Page 131
... Port B Register Register name Port B data register Port B output control register Port B function register 1 Port B pull-up control register Port B input control register Base Address = 0x4000_0040 PBDATA PBCR PBFR1 PBPUP PBIE Page 111 TMPM333FDFG/FYFG/FWFG T11 Address (Base+) 0x0000 0x0004 0x0008 0x002C 0x0038 ...
Page 132
... PB7C After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PB7C-PB0C R PB6 PB5 PB4 Read as 0. Port B data register PB6C PB5C PB4C Read as 0. Output 0: Disable 1: Enable Page 112 TMPM333FDFG/FYFG/FWFG PB3 PB2 PB1 Function PB3C PB2C PB1C Function PB0 ...
Page 133
... After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-3 − R Read PB2F1 R/W 0: PORT 1: TRST 1 PB1F1 R/W 0: PORT 1: TDI 0 PB0F1 R/W 0: PORT 1: TDO/SWV PB2F1 Function Page 113 TMPM333FDFG/FYFG/FWFG PB1F1 PB0F1 ...
Page 134
... PB7IE After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PB7IE-PB0IE R PB6UP PB5UP PB4UP Read as 0. Pull-up 0: Disable 1: Enable PB6IE PB5IE PB4IE Read as 0. Input 0: Disable 1: Enable Page 114 TMPM333FDFG/FYFG/FWFG PB3UP PB2UP PB1UP Function PB3IE PB2IE PB1IE Function PB0UP ...
Page 135
... Type − − 8.2.3.2 Port C Register Register name Port C data register Port C pull-up control register Port C input control register − − T17 T17 Base Address = 0x4000_0080 PCDATA PCPUP PCIE Page 115 TMPM333FDFG/FYFG/FWFG 1 0 T17 T17 Address (Base+) 0x0000 0x002C 0x0038 ...
Page 136
... After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-4 − R 3-0 PC3UP-PC0UP R Read as 0. Port C data register PC3UP Read as 0. Pull-up 0: Disable 1: Enable Page 116 TMPM333FDFG/FYFG/FWFG PC3 PC2 PC1 Function PC2UP PC1UP Function PC0 PC0UP 0 ...
Page 137
... PCIE (Port C input control register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-4 − R Read as 0. 3-0 PC3IE-PC0IE R/W input 0: Disable 1: Enable PC3IE PC2IE Function Page 117 TMPM333FDFG/FYFG/FWFG PC1IE PC0IE ...
Page 138
... Port D Register Port D data register Port D function register 1 Port D pull-up control register Port D input control register T17 T17 T17 Register name PDDATA PDFR1 PDPUP PDIE Page 118 TMPM333FDFG/FYFG/FWFG T18 T18 T18 Base Address = 0x4000_00C0 Address (Base+) 0x0000 0x0008 0x002C 0x0038 0 T18 ...
Page 139
... After reset 0 0 Bit Bit Symbol Type 31-4 − R Read PD3F1 R/W 0: PORT 1: TB6IN1 2 PD2F1 R/W 0: PORT 1: TB6IN0 1 PD1F1 R/W 0: PORT 1: TB5IN1 0 PD0F1 R/W 0: PORT 1: TB5IN0 PD5 PD4 PD3 Function PD3F1 PD2F1 Function Page 119 TMPM333FDFG/FYFG/FWFG PD2 PD1 PD0 PD1F1 PD0F1 ...
Page 140
... PD7IE After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PD7IE-PD0IE R PD6UP PD5UP PD4UP Read as 0. Pull-up 0: Disable 1: Enable PD6IE PD5IE PD4IE Read as 0. Input 0: Disable 1: Enable Page 120 TMPM333FDFG/FYFG/FWFG PD3UP PD2UP PD1UP Function PD3IE PD2IE PD1IE Function PD0UP ...
Page 141
... Port E function register 2 Port E open drain control register Port E pull-up control register Port E input control register T10 T4 T16 Base Address = 0x4000_0100 PEDATA PECR PEFR1 PEFR2 PEOD PEPUP PEIE Page 121 TMPM333FDFG/FYFG/FWFG T10 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0028 0x002C 0x0038 ...
Page 142
... After reset 0 Bit Bit Symbol Type 31-7 − R 6-0 PE6C-PE0C R PE6 PE5 PE4 Read as 0. Port E data register PE6C PE5C PE4C Read as 0. Output 0: Disable 1: Enable Page 122 TMPM333FDFG/FYFG/FWFG PE3 PE2 PE1 Function PE3C PE2C PE1C Function PE0 ...
Page 143
... R Read PE6F1 R/W 0: PORT 1: SCLK1 5 PE5F1 R/W 0: PORT 1: RXD1 4 PE4F1 R/W 0: PORT 1: TXD1 3 PE3F1 R/W 0: PORT 1: Reserved 2 PE2F1 R/W 0: PORT 1: SCLK0 1 PE1F1 R/W 0: PORT 1: RXD0 0 PE0F1 R/W 0: PORT 1: TXD0 PE5F1 PE4F1 PE3F1 Function Page 123 TMPM333FDFG/FYFG/FWFG PE2F1 PE1F1 PE0F1 ...
Page 144
... After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-7 − R 6-0 PE6OD- R/W PE0OD PE6F2 - - Read PORT 1: CTS1 Read PORT 1: CTS0 Read PE6OD PE5OD PE4OD Read CMOS 1: Open-drain Page 124 TMPM333FDFG/FYFG/FWFG PE2F2 - Function PE3OD PE2OD PE1OD Function PE0OD 0 ...
Page 145
... After reset bit symbol - PE6IE After reset 0 0 Bit Bit Symbol Type 31-7 − R Read as 0. 6-0 PE6IE-PE0IE R/W Input 0: Disable 1: Enable PE5UP PE4UP PE3UP Function PE5IE PE4IE PE3IE Function Page 125 TMPM333FDFG/FYFG/FWFG PE2UP PE1UP PE0UP PE2IE PE1IE PE0IE ...
Page 146
... Port F open drain control register Port F pull-up control register Port F input control register T13 T13 T13 Register name PFDATA PFCR PFFR1 PFFR2 PFOD PFPUP PFIE Page 126 TMPM333FDFG/FYFG/FWFG T16 T4 Base Address = 0x4000_0140 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0028 0x002C 0x0038 0 T10 ...
Page 147
... After reset bit symbol PF7C PF6C After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PF7C-PF0C R/W Output 0: Disable 1: Enable PF5 PF4 PF3 Function PF5C PF4C PF3C Function Page 127 TMPM333FDFG/FYFG/FWFG PF2 PF1 PF0 PF2C PF1C PF0C ...
Page 148
... PF6F1 R/W 5 PF5F1 R/W 4 PF4F1 R/W 3 PF3F1 R/W 2 PF2F1 R/W 1 PF1F1 R/W 0 PF0F1 R PF6F1 PF5F1 PF4F1 Read PORT 1: INT5 0: PORT 1: SCK1 0: PORT 1: SI1/SCL1 0: PORT 1: SO1/SDA1 0: PORT 1: Reserved 0: PORT 1: SCLK2 0: PORT 1: RXD2 0: PORT 1: TXD2 Page 128 TMPM333FDFG/FYFG/FWFG PF3F1 PF2F1 PF1F1 Function PF0F1 0 ...
Page 149
... After reset bit symbol - - After reset bit symbol PF7OD PF6OD After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PF7OD-PF0OD R/W 0: CMOS 1: Open-drain Function PF5OD PF4OD PF3OD Function Page 129 TMPM333FDFG/FYFG/FWFG PF2F2 - - PF2OD PF1OD PF0OD ...
Page 150
... PF7IE After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PF7IE-PF0IE R PF6UP PF5UP PF4UP Read as 0. Pull-up 0: Disable 1: Enable PF6IE PF5IE PF4IE Read as 0. Input 0: Disable 1: Enable Page 130 TMPM333FDFG/FYFG/FWFG PF3UP PF2UP PF1UP Function PF3IE PF2IE PF1IE Function PF0UP ...
Page 151
... Port G open drain control register Port G pull-up control register Port G input control register Note:Access to the "reserved" areas is prohibited T13 T13 T8 T13 PGDATA PGCR PGFR1 - PGOD PGPUP PGIE Page 131 TMPM333FDFG/FYFG/FWFG T13 T13 Base Address = 0x4000_0180 Address (Base+) 0x0000 0x0004 0x0008 0x0010 0x0028 0x002C 0x0038 ...
Page 152
... PG7C After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PG7C-PG0C R PG6 PG5 PG4 Read as 0. Port G data register PG6C PG5C PG4C Read as 0. Output 0: Disable 1: Enable Page 132 TMPM333FDFG/FYFG/FWFG PG3 PG2 PG1 Function PG3C PG2C PG1C Function PG0 ...
Page 153
... R/W 0: PORT 1: TB8OUT 6 PG6F1 R/W 0: PORT 1: SCK2 5 PG5F1 R/W 0: PORT 1: SI2/SCL2 4 PG4F1 R/W 0: PORT 1: SO2/SDA2 3 PG3F1 R/W 0: PORT 1: INT4 2 PG2F1 R/W 0: PORT 1: SCK0 1 PG1F1 R/W 0: PORT 1: SI0/SCL0 0 PG0F1 R/W 0: PORT 1: SO0/SDA0 PG5F1 PG4F1 PG3F1 Function Page 133 TMPM333FDFG/FYFG/FWFG PG2F1 PG1F1 PG0F1 ...
Page 154
... PG7UP After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PG7UP- R/W PG0UP PG6OD PG5OD PG4OD Read CMOS 1: Open-drain PG6UP PG5UP PG4UP Read as 0. Pull-up 0: Disable 1: Enable Page 134 TMPM333FDFG/FYFG/FWFG PG3OD PG2OD PG1OD Function PG3UP PG2UP PG1UP Function PG0OD ...
Page 155
... After reset bit symbol - - After reset bit symbol - - After reset bit symbol PG7IE PG6IE After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PG7IE-PG0IE R/W Input 0: Disable 1: Enable PG5IE PG4IE PG3IE Function Page 135 TMPM333FDFG/FYFG/FWFG PG2IE PG1IE PG0IE ...
Page 156
... Port H output control register Port H function register 1 Reserved Port H pull-up control register Port H input control register Note:Access to the "reserved" areas is prohibited Register name PHDATA PHCR PHFR1 - PHPUP PHIE Page 136 TMPM333FDFG/FYFG/FWFG Base Address = 0x4000_01C0 Address (Base+) 0x0000 0x0004 0x0008 0x0010 0x002C 0x0038 0 T5 ...
Page 157
... After reset bit symbol PH7C PH6C After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PH7C-PH0C R/W Output 0: Disable 1: Enable PH5 PH4 PH3 Function PH5C PH4C PH3C Function Page 137 TMPM333FDFG/FYFG/FWFG PH2 PH1 PH0 PH2C PH1C PH0C ...
Page 158
... PH6F1 R/W 5 PH5F1 R/W 4 PH4F1 R/W 3 PH3F1 R/W 2 PH2F1 R/W 1 PH1F1 R/W 0 PH0F1 R PH6F1 PH5F1 PH4F1 Read PORT 1: TB3IN1 0: PORT 1: TB3IN0 0: PORT 1: TB2IN1 0: PORT 1: TB2IN0 0: PORT 1: TB1IN1 0: PORT 1: TB1IN0 0: PORT 1: TB0IN1 0: PORT 1: TB0IN0 Page 138 TMPM333FDFG/FYFG/FWFG PH3F1 PH2F1 PH1F1 Function PH0F1 0 ...
Page 159
... After reset bit symbol PH7IE PH6IE After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PH7IE-PH0IE R/W Input 0: Disable 1: Enable PH5UP PH4UP PH3UP Function PH5IE PH4IE PH3IE Function Page 139 TMPM333FDFG/FYFG/FWFG PH2UP PH1UP PH0UP PH2IE PH1IE PH0IE ...
Page 160
... Port I output control register Port I function register 1 Reserve Port I pull-up control register Port I input control register Note:Access to the "reserved" areas is prohibited Register name PIDATA PICR PIFR1 - PIPUP PIIE Page 140 TMPM333FDFG/FYFG/FWFG Base Address = 0x4000_0200 Address (Base+) 0x0000 0x0004 0x0008 0x0010 0x002C 0x0038 0 T9 ...
Page 161
... After reset bit symbol PI7C PI6C After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PI7C-PI0C R/W Output 0: Disable 1: Enable PI5 PI4 PI3 Function PI5C PI4C PI3C Function Page 141 TMPM333FDFG/FYFG/FWFG PI2 PI1 PI0 PI2C PI1C PI0C ...
Page 162
... PI6F1 R/W 5 PI5F1 R/W 4 PI4F1 R/W 3 PI3F1 R/W 2 PI2F1 R/W 1 PI1F1 R/W 0 PI0F1 R PI6F1 PI5F1 PI4F1 Read PORT 1: TB4IN1 0: PORT 1: TB4IN0 0: PORT 1: TB5OUT 0: PORT 1: TB4OUT 0: PORT 1: TB3OUT 0: PORT 1: TB2OUT 0: PORT 1: TB1OUT 0: PORT 1: TB0OUT Page 142 TMPM333FDFG/FYFG/FWFG PI3F1 PI2F1 PI1F1 Function PI0F1 0 ...
Page 163
... After reset bit symbol PI7IE PI6IE After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PI7IE-PI0IE R/W Input 0: Disable 1: Enable PI5UP PI4UP PI3UP Function PI5IE PI4IE PI3IE Function Page 143 TMPM333FDFG/FYFG/FWFG PI2UP PI1UP PI0UP PI2IE PI1IE PI0IE ...
Page 164
... Port J output control register Port J function register 1 Reserved Port J pull-up control register Port J input control register Note:Access to the "reserved" areas is prohibited Register name PJDATA PJCR PJFR1 - PJPUP PJIE Page 144 TMPM333FDFG/FYFG/FWFG Base Address = 0x4000_0240 Address (Base+) 0x0000 0x0004 0x0008 0x0010 0x002C 0x0038 0 T7 ...
Page 165
... After reset bit symbol PJ7C PJ6C After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PJ7C-PJ0C R/W Output 0: Disable 1: Enable PJ5 PJ4 PJ3 Function PJ5C PJ4C PJ3C Function Page 145 TMPM333FDFG/FYFG/FWFG PJ2 PJ1 PJ0 PJ2C PJ1C PJ0C ...
Page 166
... PJ6F1 R/W 5 PJ5F1 R/W 4 PJ4F1 R/W 3 PJ3F1 R/W 2 PJ2F1 R/W 1 PJ1F1 R/W 0 PJ0F1 R PJ6F1 PJ5F1 PJ4F1 Read PORT 1: INT7 0: PORT 1: INT6 0: PORT 1: TB7OUT 0: PORT 1: TB6OUT 0: PORT 1: INT3 0: PORT 1: INT2 0: PORT 1: INT1 0: PORT 1: INT0 Page 146 TMPM333FDFG/FYFG/FWFG PJ3F1 PJ2F1 PJ1F1 Function PJ0F1 0 ...
Page 167
... After reset bit symbol PJ7IE PJ6IE After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PJ7IE-PJ0IE R/W Input 0: Disable 1: Enable PJ5UP PJ4UP PJ3UP Function PJ5IE PJ4IE PJ3IE Function Page 147 TMPM333FDFG/FYFG/FWFG PJ2UP PJ1UP PJ0UP PJ2IE PJ1IE PJ0IE ...
Page 168
... Port K function register 1 Port K function register 2 Port K pull-up control register Port K input control register − − − Register name PKDATA PKCR PKFR1 PKFR2 PKPUP PKIE Page 148 TMPM333FDFG/FYFG/FWFG − T9 T15 T14 Base Address = 0x4000_0280 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x002C 0x0038 0 ...
Page 169
... After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-3 − R Read as 0. 2-0 PK2C-PK0C R/W Output 0: Disable 1: Enable PK2 Function PK2C Function Page 149 TMPM333FDFG/FYFG/FWFG PK1 PK0 PK1C PK0C ...
Page 170
... After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-3 − PK2F1 R/W 1 PK1F1 R/W 0 PK0F1 R Read PORT 1: TB9OUT 0: PORT 1: SCOUT 0: PORT 1: Reserved Page 150 TMPM333FDFG/FYFG/FWFG PK2F1 PK1F1 Function PK0F1 0 ...
Page 171
... After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-3 − R Read as 0. 2-1 PK2UP-PK1UP R/W Pull-up 0: Disable 1: Enable 0 − R Read Function PK2UP Function Page 151 TMPM333FDFG/FYFG/FWFG PK1F2 - PK1UP - ...
Page 172
... PKIE (Port K input control register) 31 bit symbol - After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-3 − R 2-0 PK2IE-PK0IE R Read as 0. Input 0: Disable 1: Enable Page 152 TMPM333FDFG/FYFG/FWFG PK2IE PK1IE Function PK0IE 0 ...
Page 173
... Output − R − Input − R − − ο R − − ο R − Page 153 TMPM333FDFG/FYFG/FWFG Programma- ble Note open-drain − − − ο BOOT input enabled during − reset − − ο − ο Function output triggered by − enable signal Function output triggered by − ...
Page 174
... Block Diagrams of Ports 8.3.2 Type T1 (Pull-up Control) (Output Controll) (Output Latch) (Input Control) Drive Disable in STOP Mode (Set by <DRVE>) PxPUP PxCR PxDATA PxIE 0 1 Port Read Figure 8-1 Port Type T1 Page 154 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 175
... Type T2 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Function Input Drive Disable In STOP Mode Set by <DRVE> Figure 8-2 Port type T2 Page 155 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 176
... Block Diagrams of Ports 8.3.4 Type T3 (Function Control) Function Input Drive Disable in STOP Mode (Set by <DRVE>) PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 PxDATA (Output Latch) PxIE (Input Control Port Read Figure 8-3 Port Type T3 Page 156 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 177
... Type T4 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open Drain Control) PxIE (Input Control) Port Read Function Input Drive Disable In STOP Mode Set by <DRVE> Figure 8-4 Port Type T4 Page 157 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 178
... Block Diagrams of Ports 8.3.6 Type5 T5 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Function Input BOOT Drive Disable in STOP Mode (Set by <DRVE> Figure 8-5 Port Type T5 Page 158 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 179
... Type T6 PxPDN (Pull-down Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Function Input Drive Disable In STOP Mode (Set by <DRVE> Figure 8-6 Port Type T6 Page 159 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 180
... Block Diagrams of Ports 8.3.8 Type T7 Interrupt Input Drive Disable In STOP Mode (Set by <DRVE>) PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control Port Read Noise Filter ( ) Figure 8-7 Port Type T7 Page 160 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 181
... Type T8 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) Port Read Interrupt Noise Filter Input ( ) Drive Disable In STOP Mode Set by <DRVE> Figure 8-8 Port Type T8 Page 161 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 182
... Block Diagrams of Ports 8.3.10 Type T9 (Pull-up Control) (Output Control) (Function Control) (Output Latch) (Input Control) Port Read Drive Disable In STOP Mode (Set by <DRVE> PxPUP PxCR PxFR1 1 Function Output PxDATA 0 PxIE 0 1 Figure 8-9 Port Type T9 Page 162 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 183
... Type T10 PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) Port Read Drive Disable in STOP Mode (Set by <DRVE>) 1 Function Output Figure 8-10 Port Type T10 Page 163 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 184
... Control) (Output Control) (Function Control) (Output Latch) (Input Control) Port Read Drive Disable in STOP Mode (Set by <DRVE>) PxPUP PxCR Function Output Enable 1 0 PxFR1 1 Function Output PxDATA 0 PxIE 0 1 Figure 8-11 Port Type T11 Page 164 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 185
... PxPUP (Pull-up Control) PxCR (Output Control) Function Output Enable PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Function Input Drive Disable in STOP Mode (Set by <DRVE> Function 1 Output Figure 8-12 Port Type T12 Page 165 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 186
... PxPUP (Pull-up Control) PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) Port Read Function Input Drive Disable in STOP Mode (Set by <DRVE>) 1 Function Output Figure 8-13 Port Type T13 Page 166 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 187
... Type T14 PxCR (Output Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Function Input Drive Disable in STOP Mode (Set by <DRVE>) Function 1 Output N-chanel 0 Open-drain 0 1 Figure 8-14 Port Type T14 Page 167 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 188
... Control) PxCR (Output Control) PxFR2 (Function Control) PxFR1 (Function Control) PxDATA (Output Latch) PxIE (Input Control) Port Read Drive Disable in STOP Mode Set by <DRVE> Function 1 Function 1 Output2 Output1 0 0 Figure 8-15 Port Type T15 Page 168 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 189
... Control) PxFR2 (Function Control) PxFR1 (Function Control) PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) Port Read Function Input1 Function Input2 Drive Disable in STOP Mode Set by <DRVE> Function 1 Output1 Figure 8-16 Port Type T16 Page 169 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 190
... Block Diagrams of Ports 8.3.18 Type T17 Analog Input Drive Disable in STOP Mode PxPUP (Pull-up Control) PxIE (Input Control) Port Read Figure 8-17 Port Type T17 Page 170 TMPM333FDFG/FYFG/FWFG <DRVE> RESET Input Port ...
Page 191
... Type T18 PxPUP (Pull-up Control) PxFR1 (Function Control) PxIE (Input Control) Port Read Function Input Analog Input Drive Disable in STOP Mode Set by <DRVE>) Figure 8-18 Port TypeT18 Page 171 TMPM333FDFG/FYFG/FWFG RESET I/O Port ...
Page 192
... Output Port T6 TCK(Input)/ ・ SWCLK(Input) Input Port T9 Output Port TRACECLK(Output) Input Port T9 Output Port TRACEDATA0(Output) Input Port T9 Output Port TRACEDATA1(Output) Input Port T9 Output Port TRACEDATA2(Output) Input Port T9 Output Port TRACEDATA3(Output) Input Port T1 Output Port Page 172 TMPM333FDFG/FYFG/FWFG PACR PAFR1 PAPUP PAPDN PAIE ...
Page 193
... Output Port TRST(Input) Input Port PB3 T1 Output Port Input Port PB4 T1 Output Port Input Port PB5 T1 Output Port Input Port PB6 T1 Output Port Input Port PB7 T1 Output Port After re- Function PBCR PBFR1 set ・ ・ ・ Page 173 TMPM333FDFG/FYFG/FWFG PBPUP PBIE ...
Page 194
... T18 TB6IN0(Input) Analog Input Input Port T18 TB6IN1(Input) Analog Input Input Port T17 Analog Input Input Port T17 Analog Input Input Port T17 Analog Input Input Port T17 Analog Input Page 174 TMPM333FDFG/FYFG/FWFG After re- PCPUP PCIE set x 1 ・ ・ ・ ...
Page 195
... Output Port PE2 T16 SCLK0(Input) SCLK0(Output) CTS0(Input) Input Port PE3 T4 Output Port Input Port PE4 T10 Output Port TXD1(Output) Input Port PE5 T4 Output Port RXD1(Input) Input Port Output Port PE6 T16 SCLK1(Input) SCLK1(Output) CTS1(Input) TMPM333FDFG/FYFG/FWFG After re- PECR PEFR1 PEFR2 PEOD set ...
Page 196
... Input Port 0 Output Port 1 SCLK2(Input) 0 SCLK2(Output) 1 CTS2(Input) 0 Input Port 0 Output Port 1 Input Port 0 Output Port 1 SO1(Output) 1 SDA1(Input/Output) 1 Input Port 0 Output Port 1 SI1(Input) 0 SCL1(Input/Output) 1 Input Port 0 Output Port 1 SCK1(Input) 0 SCK1(Output) 1 Input Port 0 Output Port 1 INT5(Input) 0 Page 176 TMPM333FDFG/FYFG/FWFG PFFR1 PFFR2 PFOD PFPUP PFIE ...
Page 197
... Input Port Output Port PG4 T13 SO2(Output) SDA2(Input/Output) Input Port Output Port PG5 T13 SI2(Input) SCL2(Input/Output) Input Port Output Port PG6 T13 SCK2(Input) SCK2(Output) Input Port PG7 T10 Output Port TB8OUT(Output) After re- Function PGCR PGFR1 set Page 177 TMPM333FDFG/FYFG/FWFG PGOD PGPUP PGIE ...
Page 198
... Input Port T3 Output Port TB0IN1(Input) Input Port T3 Output Port TB1IN0(Input) Input Port T3 Output Port TB1IN1(Input) Input Port T3 Output Port TB2IN0(Input) T3 Input Port Output Port TB2IN1(Input) T3 Input Port Output Port TB3IN0(Input) T3 Input Port Output Port TB3IN1(Input) Page 178 TMPM333FDFG/FYFG/FWFG PHCR PHFR1 PHPUP PHIE ...
Page 199
... TB2OUT(Output) Input Port PI3 T9 Output Port TB3OUT(Output) Input Port PI4 T9 Output Port TB4OUT(Output) Input Port PI5 T9 Output Port TB5OUT(Output) Input Port PI6 T3 Output Port TB4IN0(Input) PI7 Input Port T3 Output Port TB4IN1(Input) Function After re- PICR PIFR1 set Page 179 TMPM333FDFG/FYFG/FWFG PIPUP PIIE ...
Page 200
... Input Port T7 Output Port INT1(Input) Input Port T7 Output Port INT2(Input) Input Port T7 Output Port INT3(Input) Input Port T9 Output Port TB6OUT(Output) Input Port T9 Output Port TB7OUT(Output) Input Port T7 Output Port INT6(Input) Input Port T7 Output Port INT7(Input) Page 180 TMPM333FDFG/FYFG/FWFG PJCR PJFR1 PJPUP PJIE ...