TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 435

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

15.3.1.6
Table 15-15 Flash Memory Access from the Internal CPU
Read
Read/Reset
ID-Read
Automatic page program-
ming
Automatic chip erase
Auto Block erase
Protection bit program-
ming
Protection bit erase
Command sequence
cycle of the Read/reset command, and the fifth bus cycle of the ID-Read command. Bus write cycles are
executed by 32-bit (word) data transfer commands. (In the following table, only lower 8 bits data are shown.)
for the address [15:8] of the normal command in the Table 15-16.
Table 15-15 shows the addresses and the data of each command of flash memory.
Bus cycles are "bus write cycles" except for the second bus cycle of the Read command, the fourth bus
See Table 15-16 for the detail of the address bit configuration. Use a value of "Addr." in the Table 15-15
Supplementary explanation
Note:Always set "0" to the address bits [1:0] in the entire bus cycle.
List of Command Sequences
・ RA: Read address
・ RD: Read data
・ IA: ID address
・ ID: ID data
・ PA: Program page address
・ BA: Block address
・ PBA: Protection bit address
PD: Program data (32 bit data)
After the fourth bus cycle, enter data in the order of the address for a page.
First bus cy-
0x54XX
0x54XX
0x54XX
0x54XX
0x54XX
0x54XX
0x54XX
Addr.
0xXX
0xAA
0xAA
0xAA
0xAA
0xAA
0xAA
0xAA
0xF0
Data
cle
Second bus
0xAAXX
0xAAXX
0xAAXX
0xAAXX
0xAAXX
0xAAXX
0xAAXX
Addr.
cycle
0x55
0x55
0x55
0x55
0x55
0x55
0x55
Data
−
−
Third bus cy-
Page 415
0x54XX
0x54XX
0x54XX
0x54XX
0x54XX
0x54XX
0x54XX
Addr.
0xF0
0x90
0xA0
0x80
0x80
0x9A
0x6A
Data
cle
−
−
Fourth bus
0x54XX
0x54XX
0x54XX
0x54XX
Addr.
0xAA
0xAA
0xAA
0xAA
cycle
0x00
Data
PD0
RD
RA
PA
IA
−
−
Fifth bus cy-
0xAAXX
0xAAXX
0xAAXX
0xAAXX
Addr.
0xXX
Data
0x55
0x55
0x55
0x55
PD1
cle
PA
ID
−
−
−
−
TMPM333FDFG/FYFG/FWFG
Sixth bus cy-
0x54XX
0x54XX
0x54XX
Addr.
0x9A
0x6A
Data
0x10
0x30
PD2
cle
PA
BA
−
−
−
−
−
−
Seventh bus
Addr.
cycle
0x9A
0x6A
Data
PD3
PBA
PBA
PA
−
−
−
−
−
−
−
−
−
−