TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 413

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

5. The 5th to 16th bytes transmitted from the controller to the target board, are a 12-byte password.
6. The 17th byte is a checksum value for the password sequence (5th to 16th bytes). To calculate the
7. The 18th byte, transmitted from the target board to the controller, is an acknowledge response to
8. The 19th to 22nd bytes, transmitted from the controller the target board, indicate the start address
in which it waits for a command (the third byte) again. In this case, the upper four bits of the
acknowledge response are undefined - they hold the same values as the upper four bits of the
previously issued command. When the SIO0 is configured for I/O Interface mode, the boot pro-
gram does not check for a receive error.
echoes it back to the controller. When the RAM Transfer command was received, the boot program
echoes back a value of 0x10 and then branches to the RAM Transfer routine. Once this branch is
taken, password verification is done. Password verification is detailed in a later section "Pass-
word". If the 3rd byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the
controller and returns to the state in which it waits for a command (the third byte) again. In this
case, the upper four bits of the acknowledge response are undefined - they hold the same values
as the upper four bits of the previously issued command.
Each byte is compared to the contents of following addresses in the flash memory. The verification
is started with the 5th byte and the smallest address in the designated area. If the password veri-
fication fails, the RAM Transfer routine sets the password error flag.
checksum value for the 12-byte password, add the 12 bytes together, drop the carries and take the
two’s complement of the total sum. Transmit this checksum value from the controller to the target
board. The checksum calculation is described in details in a later section "Checksum Calculation".
the 5th to 17th bytes. First, the RAM Transfer routine checks for a receive error in the 5th to 17th
bytes. If there was a receive error, the boot program sends back 0x18 (bit 3) and returns to the
state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of
the acknowledge response are the same as those of the previously issued command (i.e., 1). When
the SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a
receive error.
Adding the series of the 5th to 16th bytes must result in 0x00 (with the carry dropped). If it is not
0x00, one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer
routine sends back 0x11 to the controller and returns to the state in which it waits for a command
(i.e., the 3rd byte) again.
lowing two cases are treated as a password error. In these cases, the RAM Transfer routine sends
back 0x11 (bit 0) to the controller and returns to the state in which it waits for a command (i.e.,
the 3rd byte) again.
acknowledge response (0x10) to the controller.
of the RAM region where subsequent data (e.g., a flash programming routine) should be stored.
The 19th byte corresponds to bits 31.24 of the address and the 22nd byte corresponds to bits 7.0
of the address.
・ Irrespective of the result of the password comparison, all the 12 bytes of a password in the
・ Not the entire password bytes transmitted from the controller matched those contained in
If the 3rd byte is equal to any of the command codes listed in Table 15-4, the boot program
Next, the RAM Transfer routine performs the checksum operation to ensure data integrity.
Finally, the RAM Transfer routine examines the result of the password verification. The fol-
When all the above verification has been successful, the RAM Transfer routine returns a normal
flash memory are the same value other than 0xFF.
the flash memory.
TMPM333FWFG
TMPM333FDFG
TMPM333FYFG
Product name
Page 393
0x3F87_FF04 to 0x3F87_FF0F
0x3F81_FF04 to 0x3F81_FF0F
Area
TMPM333FDFG/FYFG/FWFG