TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 265

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.11.3.6
before receiveing the next data. When overrun error is ocurred, a content of receive buffer and SCxCR<RB8>
is not lost, but a content of receive shift register is lost.
the next data into received buffer when FIFO is full . In this case, the contens of FIFO are not lost.
no meaning.
When FIFO is disabled, the overrun errorr is occurred and set overrun flag without completing data read
When FIFO is enabled, overrun error is ocurred and set overrun flag by no reading the data before moving
In the I/O interface mode with SCLK output setting, the clock output automatically stops, so this flag has
Note:When the mode is changed from I/O interface SCLK outout mode to the other mode, read SCxCR and
Overrun Error
clear overrun flag.
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TMPM333FDFG/FYFG/FWFG