TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 321

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.8
11.8.1
11.8.1.1
Control in SIO mode
Serial Clock
Figure 11-16 Maximum Transfer Frequency of External Clock Input
(1)
(2)
Internal or external clocks can be selected by programming SBIxCR1<SCK[2:0]>.
SCKx pin output
SOx pin output
Clock source
output to the outside through the SCKx pin.
received data, the SBI automatically enters a wait period. During this period, the serial clock is stopped
automatically and the next shift operation is suspended until the processing is completed.
as shown below.
In the internal clock mode, one of the seven frequencies can be selected as a serial clock, which is
At the beginning of a transfer, the SCKx pin output becomes the "High" level.
If the program cannot keep up with this serial clock rate in writing the transmit data or reading the
The SBI uses an external clock supplied from the outside to the SCKx pin as a serial clock.
For proper shift operations, the serial clock at the "High" and "Low" levels must have the pulse widths
Internal clocks
External clock (<SCK[2:0]> = "111")
SCKx
a 0
1
a
f
Figure 11-15 Automatic Wait
SCKL
a 1 a 2 a 5 a 6 a 7
2
, f
f
3
SCKL
SCKH
f
SCKH
7
> 4/fsys
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8
b
b 0 b 1
1
2
c
b 4
b 5 b 6
6
7
TMPM333FDFG/FYFG/FWFG
b 7
8
c 0
1
c 1 c 2
2
3