TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 11

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

8. Input/Output Ports
7.2 Reset Exceptions......................................................................................................................61
7.3 Non-Maskable Interrupts (NMI)..............................................................................................62
7.4 SysTick....................................................................................................................................62
7.5 Interrupts..................................................................................................................................63
7.6 Exception/Interrupt-Related Registers.....................................................................................72
8.1 Port Functions........................................................................................................................101
8.2 Port functions.........................................................................................................................106
7.5.1
7.5.2
7.6.1
7.6.2
7.6.3
8.1.1
8.1.2
8.1.3
8.1.4
8.2.1
8.2.2
7.1.2.1
7.1.2.2
7.1.2.3
7.1.2.4
7.5.1.1
7.5.1.2
7.5.1.3
7.5.1.4
7.5.1.5
7.5.1.6
7.5.2.1
7.5.2.2
7.5.2.3
7.5.2.4
7.5.2.5
7.5.2.6
7.6.2.1
7.6.2.2
7.6.2.3
7.6.2.4
7.6.2.5
7.6.2.6
7.6.2.7
7.6.2.8
7.6.2.9
7.6.2.10
7.6.2.11
7.6.2.12
7.6.2.13
7.6.2.14
7.6.2.15
7.6.2.16
7.6.2.17
7.6.3.1
7.6.3.2
7.6.3.3
7.6.3.4
7.6.3.5
7.6.3.6
8.2.1.1
8.2.1.2
8.2.1.3
8.2.1.4
8.2.1.5
8.2.1.6
8.2.1.7
8.2.1.8
8.2.2.1
Interrupt Sources................................................................................................................................................................63
Interrupt Handling..............................................................................................................................................................67
Register List.......................................................................................................................................................................72
NVIC Registers..................................................................................................................................................................73
Clock generator registers...................................................................................................................................................91
Function Lists..................................................................................................................................................................101
Port Registers Outline......................................................................................................................................................104
Port States in STOP Mode...............................................................................................................................................105
Precautions for Mode Transition between STOP and SLEEP.........................................................................................105
Port A (PA0 to PA7)........................................................................................................................................................106
Port B (PB0 to PB7).........................................................................................................................................................111
Exception Request and Detection
Exception Handling and Branch to the Interrupt Service Routine (Pre-emption)
Executing an ISR
Exception exit
Interrupt Route
Generation
Transmission
Precautions when using external interrupt pins
List of Interrupt Sources
Active level
Flowchart
Preparation
Detection by Clock Generator
Detection by CPU
CPU processing
Interrupt Service Routine (ISR)
SysTick Control and Status Register
SysTick Reload Value Register
SysTick Current Value Register
SysTick Calibration Value Register
Interrupt Set-Enable Register 1
Interrupt Set-Enable Register 2
Interrupt Clear-Enable Register 1
Interrupt Clear-Enable Register 2
Interrupt Set-Pending Register 1
CGIMCGA(CG Interrupt Mode Control Register A)
CGIMCGB(CG Interrupt Mode Control Register B)
CGIMCGC(CG Interrupt Mode Control Register C)
CGICRCG(CG Interrupt Request Clear Register)
CGNMIFLG(NMI Flag Register)
CGRSTFLG (Reset Flag Register)
Port A Circuit Type
Port A register
PADATA (Port A data register)
PACR (Port A output control register)
PAFR1 (Port A function register 1)
PAPUP (Port A pull-up control register)
PAPDN (Port A pull-down control register)
PAIE (Port A input control register)
Port B Circuit Type
Interrupt Set-Pending Register 2
Interrupt Clear-Pending Register 1
Interrupt Clear-Pending Register 2
Interrupt Priority Register
Vector Table Offset Register
Application Interrupt and Reset Control Register
System Handler Priority Register
System Handler Control and State Register
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