TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 337

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TMPM333FDFG

Manufacturer Part Number
TMPM333FDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
Manufacturer
Toshiba
Datasheets

Specifications of TMPM333FDFG

Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
512K
Rom Type
Flash
Ram (kbytes)
32K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM333FDFG
Manufacturer:
Toshiba
Quantity:
10 000
12.3.6
31-8
7
6
5
4
3-0
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit
EOCFHP
ADBFHP
HPADCE
HPADCH[3:0]
Bit Symbol
ADMOD2 (Mode Control Register 2)
EOCFHP
31
23
15
0
0
0
7
0
-
-
-
R
R
R
R/W
R/W
R/W
Type
ADBFHP
30
22
14
0
0
0
6
0
Read as 0.
Top-priority AD conversion completion flag (Note1)
0: Before or during conversion
1: Completion
Top-priority AD conversion BUSY flag
0: During conversion halts
1: During conversion
Activate top-priority conversion
0: Don't care
1: Start conversion
"0" is always read.
Write "0".
Select analog input channel when activating top-priority conversion. (See the table below)
-
-
-
HPADCE
29
21
13
0
0
0
5
0
-
-
-
Page 317
28
20
12
0
0
0
4
0
-
-
-
-
27
19
11
Function
0
0
0
3
0
-
-
-
<HPADCH[3:0]>
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
26
18
10
0
0
0
2
0
-
-
-
TMPM333FDFG/FYFG/FWFG
HPADCH
25
17
0
0
9
0
1
0
-
-
-
top-priority conversion
Analog input channel
Setting prohibited
whene xecuting
AIN10
AIN11
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
24
16
0
0
8
0
0
0
-
-
-

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