TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 112

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

7.6
Exception/Interrupt-Related Registers
14-12
11-10
9
8
7
6-4
3-2
1
0
Bit
Note 1: <EMSTx> is effective only when <EMCGx[2:0]> is set to "100" for both rising and falling edge. The active level
Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited.
EMCG1[2:0]
EMST1[1:0]
−
INT1EN
−
EMCG0[2:0]
EMST0[1:0]
−
INT0EN
Bit Symbol
used for the reset of standby can be checked by referring <EMSTx>. If interrupts are cleared with the CGICRCG
register, <EMSTx> is also cleared.
R/W
R
R
R/W
R
R/W
R
R
R/W
Type
active level setting of INT1 standby clear request. (101~111: setting prohibited)
000: "Low" level
001: "High" level
010: Falling edge
011: Rising edge
100: Both edges
active level of INT1 standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edges
Reads as undefined.
INT1 clear input
0:Disable
1: Enable
Read as 0.
active level setting of INT0 standby clear request. (101~111: setting prohibited)
000: "Low" level
001: "High" level
010: Falling edge
011: Rising edge
100: Both edges
active level of INT0 standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edges
Reads as undefined.
INT0 clear input
0:Disable
1: Enable
Page 92
Function
TMPM333FDFG/FYFG/FWFG