TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 60

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

6.3
Clock control
6.3
6.3.1
6.3.2
Clock control
(IDLE,SLEEP,STOP.)
X2 pin.
Clock System Block Diagram
Initial Values after Reset
Each clock is defined as follows:
The high-speed clock fc and the prescaler clock ΦT0 are dividable as follows.
CPU uses the following clocks. HCLK and FCLK stop in the low power consumption mode
Reset operation initializes the clock configuration as follows.
Reset operation causes all the clock configurations excluding the low-speed clock (fs) to be the same as fosc.
For example, reset operation configures fsys as 10MHz when a 10MHz oscillator is connected to the X1 or
fosc
fs
fpll
fc
fgear
fsys
fperiph
φT0
High-speed clock
Prescaler clock
HCLK,FCLK
STCLK (Systick timer)
High-speed oscillator
Low-speed oscillator
PLL (phase locked loop circuit)
High-speed clock gear
fc = fosc
fsys = fosc
φT0 = fosc
: Clock input from the X1 and X2 pins
: Clock input from the XT1 and XT2 (low-speed clock)
: Clock quadrupled by PLL
: Clock specified by CGPLLSEL<PLLSEL> (high-speed clock)
: Clock specified by CGSYSCR<GEAR[2:0]>
: Clock specified by CGCKSEL<SYSCK> (system clock)
: Clock specified by CGSYSCR<FPSEL>
: Clock specified by CGSYSCR<PRCK[2:0]> (prescaler clock)
: fc, fc/2, fc/4, fc/8
: fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16, fperiph/32
: fsys
: fosc/32
: oscillating
: oscillating
: stop
: fc (no frequency dividing)
Page 40
TMPM333FDFG/FYFG/FWFG