TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 264

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.11
Receive
10.11.3.3
10.11.3.4
10.11.3.5
the receive buffer and FIFO. So, in this mode, the overrun error flag has no meaning.
In the case of the next data can be received in the receive shift register before reading a data from the receive
buffer. The parity bit to be added in the 8-bit UART mode as well as the most significant bit in the 9-bit UART
mode will be stored in SCxCR<RB8>.
stored in FIFO. In the 8-bit UART mode, the parity bit is lost but parity error is determined and the result is
stored in SCxCR<PERR>.
function SCxMOD0 <WU> to "1." In this case, the interrupt INTRXx will be generated only when SCxCR
<RB8> is set to "1."
(1)
(2)
(3)
In the I/O interface mode and SCLK output setting, SCLK output stops when all received data is stored in
The timing of SCLK output stop and re-output depends on receive buffer and FIFO.
In spite of enabling or disabling FIFO, read the received data from the receive buffer (SCxBUF).
When receive FIFO is disabled, the buffer full flag SCxMOD2<RBFLL> is cleared to "0" by this reading.
When the receive FIFO is available, the 9-bit UART mode is prohibited because up to 8-bit data can be
In the 9-bit UART mode, the slave controller can be operated in the wake-up mode by setting the wake-up
I/O interface mode with SCLK output
Read Received Data
Wake-up Function
transfer device by hand-shake.
the receive shift register is transferred into received buffer and SCLK output is restarted.
SCxMOD0<RXE> bit too.
Stop SCLK output after receiving a data. In this mode, I/O interface can transfer each data with the
When the data in a buffer is read, SCLK output is restarted.
Stop SCLK output after receiving the data into a receive shift register and a receive buffer.
When the data is read, SCLK output is restarted.
Stop SCLK output after receiving the data into a shift register, received buffer and FIFO.
When one byte data is read, the data in the received buffer is transferred into FIFO and the data in
And if SCxFCNF<RXTXCNT>is set to "1", SCLK stops and receive operation stops with clearing
Case of single buffer
Case of double buffer
Case of FIFO
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TMPM333FDFG/FYFG/FWFG