TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 51

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

5. Reset
5.1
(WDT) and the setting <SYSRESETREQ> in the Application Interrupt and Reset Control Register.
TMPM333FDFG/FYFG/FWFG, the internal regulator requires at least 700 μs to be stable.
"Low" for a duration of time sufficiently long enough for the internal regulator and oscillator to be stable.
The case where it takes
700
oscillation
Note 1: The power supply must be raised (from 0V to 2.7V) at a speed of 0.37ms/V or slower.
Note 2: Turn on the power while the RESET pin is fixed to "Low". Release the reset while all the power supplies are
Cold reset
The TMPM333FDFG/FYFG/FWFG has three reset sources: an external reset pin (RESET), a watchdog timer
For reset from the WDT, refer to the chapter on the WDT.
For reset from <SYSRESETREQ>, refer to "Cortex-M3 Technical Reference Manual".
The power-on sequence must consider the time for the internal regulator and oscillator to be stable.In the
The time required to achieve stable oscillation varies with system. At cold reset, the external reset pin must be kept
Figure 5-1 shows the power-on sequence.
Note:Do not reset with <SYSRESETREQ> in SLOW mode.
RVDD3,
DVDD3,
AVDD3
RESET
High-speed oscillation
RESET
RESET
High-speed oscillation
s or more for stable
stabilized within operating voltage.
2.7 V
0 V
0.37ms/V
Figure 5-1 Cold Reset Sequence
(min.)
Page 31
700
s (min.)
12 cycle(min.)
TMPM333FDFG/FYFG/FWFG
12 cycle(min.)