VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 
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Power Management I/O-Space Registers
Basic Power Management Control and Status
I/O Offset 1-0 - Power Management Status ................. RWC
The bits in this register are set only by hardware and can be
reset by software by writing a one to the desired bit position.
15
Wakeup Status (WAK_STS) ................... default = 0
This bit is set when the system is in the suspend state
and an enabled resume event occurs. Upon setting
this bit, the system automatically transitions from the
suspend state to the normal working state (from C3 to
C0 for the processor).
14-12 Reserved
........................................ always reads 0
Abnormal Power-Off (APO_STS)........... default = 0
11
10
RTC Status (RTC_STS) ........................... default = 0
This bit is set when the RTC generates an alarm (on
assertion of the RTC IRQ signal).
9
Sleep Button Status (SB_STS)................. default = 0
This bit is set when the sleep button (SLPBTN# /
IRQ6 / GPI4) is pressed.
8
Power Button Status (PB_STS)............... default = 0
This bit is set when the PWRBTN# signal is asserted
LOW. If the PWRBTN# signal is held LOW for
more than four seconds, this bit is cleared and the
system will transition into the soft off state.
7-6
Reserved
........................................ always reads 0
5
Global Status (GBL_STS)........................ default = 0
This bit is set by hardware when BIOS_RLS is set
(typically by an SMI routine to release control of the
SCI/SMI lock). When this bit is cleared by software
(by writing a one to this bit position) the BIOS_RLS
bit is also cleared at the same time by hardware.
4
Bus Master Status (BM_STS) ................. default = 0
This bit is set when a system bus master requests the
system bus. All PCI master, ISA master and ISA
DMA devices are included.
........................................ always reads 0
3-1
Reserved
0
ACPI Timer Carry Status (TMR_STS) .. default = 0
rd
The bit is set when the 23
bit ACPI power management timer changes.
Revision 1.71 June 9, 2000
I/O Offset 3-2 - Power Management Enable .................. RW
The bits in this register correspond to the bits in the Power
Management Status Register at offset 1-0.
15
14-12 Reserved
11
10
9
8
7-6
5
4
3-1
0
(31st) bit of the 24 (32)
-90-
Reserved
........................................always reads 0
........................................always reads 0
........................................always reads 0
Reserved
RTC Enable (RTC_EN)............................ default = 0
This bit may be set to trigger either an SCI or an SMI
(depending on the setting of the SCI_EN bit) to be
generated when the RTC_STS bit is set.
Sleep Button Enable (SB_EN) .................default = 0
This bit may be set to trigger either an SCI or SMI
when the SB_STS bit is set.
Power Button Enable (PB_EN) ...............default = 0
This bit may be set to trigger either an SCI or an SMI
(depending on the setting of the SCI_EN bit) to be
generated when the PB_STS bit is set.
Reserved
........................................always reads 0
Global Enable (GBL_EN).........................default = 0
This bit may be set to trigger either an SCI or an SMI
(depending on the setting of the SCI_EN bit) to be
generated when the GBL_STS bit is set.
Reserved
........................................always reads 0
........................................always reads 0
Reserved
ACPI Timer Enable (TMR_EN) ..............default = 0
This bit may be set to trigger either an SCI or an SMI
(depending on the setting of the SCI_EN bit) to be
generated when the TMR_STS bit is set.
Power Management I/O-Space Registers
VT82C686B