SI3021-KS ETC-unknow, SI3021-KS Datasheet
SI3021-KS
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SI3021-KS Summary of contents
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... MCLK OFHK 16 FSYNC 2 RGDT/FSD 15 SCLK SDO GND 5 12 SDI C1A 6 11 FC/RGDT RESET AOUT 9 8 Si3021 (TSSOP) SDO SDI 2 SCLK 15 FC/RGDT FSYNC 3 14 RESET MCLK 4 13 AOUT OFHK RGDT/FSD 11 6 C1A GND V 8 ...
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Rev. 1.2 ...
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... On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Loop Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Multiple Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Appendix—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Pin Descriptions: Si3021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Pin Descriptions: Si3012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SOIC Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 TSSOP Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Rev. 1.2 Si3035 Page 3 ...
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... Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 3. The digital supply can operate from either 3 5.0 V. The Si3021 supports interface to 3.3 V logic when D operating from 3.3 V. The 3.3 V operation applies to both the serial port and the digital signals RGDT, OFHK, RESET, M0, and M1 ...
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Table 3. DC Characteristics ±5 ±5 70°C for K-Grade Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level ...
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Table 5. AC Characteristics (V = Charge Pump +3.3 V ± 0 Parameter 1 Sample Rate PLL1 Output Clock Frequency Transmit Frequency Response Receive Frequency Response 2 Transmit Full Scale ...
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... Table 6. Absolute Maximum Ratings Parameter DC Supply Voltage Input Current, Si3021 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Switching Characteristics— ...
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Table 8. Switching Characteristics—Serial Interface (DCE = Charge Pump 3 Parameter Cycle time, SCLK SCLK duty cycle Delay time, SCLK to FSYNC Delay time, SCLK ...
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Table 9. Switching Characteristics—Serial Interface (DCE = 1, FSD = Charge Pump 3 1,2 Parameter Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK to FSYNC Delay Time, SCLK ...
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Table 10. Switching Characteristics—Serial Interface (DCE = 1, FSD = Charge Pump 3 1,2 Parameter Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK to ...
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Table 11. Digital FIR Filter Characteristics—Transmit and Receive (V = Charge Pump ±5%, Sample Rate = 8 kHz Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay ...
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Input Frequency—Hz Figure 6. FIR Receive Filter Response Input Frequency—Hz Figure 7. FIR Receive Filter Passband Ripple For Figures 6–9, all filter plots apply to a sample rate kHz. The filters scale ...
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Input Frequency—Hz Figure 10. IIR Receive Filter Response Input Frequency—Hz Figure 11. IIR Receive Filter Passband Ripple For Figures 10–13, all filter plots apply to a sample rate kHz. The filters scale with the sample rate ...
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Input Frequency—Hz Figure 14. IIR Receive Group Delay 14 Input Frequency—Hz Figure 15. IIR Transmit Group Delay Rev. 1.2 ...
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... C1A RESETb RESET AOUT C1 Si3021 SOIC Pinout AOUT C30 D4 M1 BAV99 C2 C4 Note not required when Vcc=3.3 V and the charge pump is enabled (CPE = 1). Note 2: If JATE support is not required, R21, C12 and C23 may be removed (R21 is effectively 0 ohms) and R4 should be changed to a 604 ohm, 1 ...
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... D 16 Value Novacap, Venkel, Johanson, Murata, Novacap, Johanson, Murata, Panasonic, SMEC Novacap, Venkel, Johanson, Murata, Panasonic, SMEC Diodes, Inc., OnSemiconductor, Fairchild Teccor, ST Microelectronics, Microsemi, TI Si3021 Si3012 Diodes, Inc., OnSemiconductor, Fairchild must be 4. can be installed with A Rev. 1.2 Supplier(s) Panasonic, SMEC Central Semiconductor ...
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Analog Output Figure 17 illustrates an optional application circuit to support the analog output capability of the Si3035 for call progress monitoring purposes. The ARM bits in Register 6 allow the receive path to be attenuated by 0 dB, –6 ...
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... ID data are communicated through this barrier. The ISOcap inter-chip communication is disabled by default. To enable it, the PDL bit in Register 6 must be Si3035 cleared. No communication between the Si3021 and Si3012 can occur until this bit is cleared. The clock Devices generator must be programmed to an acceptable sample rate prior to clearing the PDL bit ...
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... ONHM bit (Register 5, bit 3). This bit must be cleared at the conclusion of the receipt of the caller ID data and prior to the next ring burst. The Si3021 can support a wake-up-on-ring function using the RGDT signal. Refer to "Power Management" on page 24 for more details ...
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... The digital interface consists of a single, synchronous serial link which communicates both telephony and control data. In Serial mode the Si3021 operates as a master, where the master clock (MCLK input, the serial data clock (SCLK output, and the frame sync signal (FSYNC output ...
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Com m unications Fram e 1 (CF1) FSYNC Prim ary Secondary FC 0 D15–D0 Secondary SDI XMT Data Data Secondary SDO RCV Data Data 16 SCLKS 128 SCLKS 256 SCLKS Figure 20. Hardware FC Secondary Request FSYNC (m ode 0) ...
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... MCLK should be from a clean source, preferably directly from a crystal with a constant frequency and no dropped pulses. In serial mode 2, the Si3021 operates as a slave device. The clock generator is configured (by default) to set the SCLK output equal to the MCLK input. The net effect is the clock generator multiplies the MCLK input by 20. For further details of slave mode operation, refer to " ...
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Table 17. N2, M2 Values (CGM = (Hz) N2 7200 2 8000 9 8229 7 8400 6 9000 4 9600 3 10286 7 The main design consideration is the generation of a base frequency, defined as the ...
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... The most common mode of operation is the normal operation. In this mode, the PDL and PDN bits are cleared. The Si3021 is fully operational and the ISOcap link is passing information between the Si3021 and the Si3012. The clock generator must be programmed to a valid sample rate prior to entering this mode. ...
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AOUT signal can be set to –20 dB, –26 dB, –32 dB, or mute. The receive portion of the AOUT signal can be set to 0 dB, –6 dB, –12 dB, or mute. Figure 17 on page 17 illustrates a ...
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signalling, the master device will have a unique setting relative to the slave devices. The DSP can use this information to determine which FSYNC marks the beginning of a sequence of data transfers. The delayed frame ...
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... DSP SCLK SDO SDI FSYNC INT0 47 k Figure 25. Typical Connection for Master/Slave Operation (e.g., Data/Fax/Voice Modem) MCLK Si3021 MCLK SCLK SDI SDO FSYNC FC/RGDT RGDT/FSD + Si3000 SCLK MCLK FSYNC SDI SDO Voice Codec Rev. 1.2 Si3035 VCC ...
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Master Serial Mode 1 Reg 14: NSLV = 1 , SSEL = 2, FSD = 0, DCE = 1 Slave 1 Serial Mode 2 Reg 14 Reset valu es: NSLV = 1, SSEL = 3, FSD ...
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Master Serial Mode 1 Reg 14: NSLV = 7, SSEL = 2, FSD = 1, DCE = 1 Serial Mode 2 Slave 1 Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1 Primary ...
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Master Serial Mode 0 Reg 14: NSLV = 1 , SSEL = 2, FSD = 0, DCE = 1 Slave 1 Serial Mode 2 Reg 14 Reset valu es: NSLV = 1, SSEL = 3, FSD ...
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... Figure 30. Typical Connection for Multiple Si3035s Rev. 1.2 Si3035 MCLK Si3021–M aster MCLK SCLK SDI SDO FSYNC FC/RGDT RGDT/FSD VCC M1 M0 Si3021–Slave 1 MCLK SCLK FSYNC SDI SDO RGDT/FSD VCC M1 M0 Si3021–Slave 2 MCLK SCLK FSYNC SDI SDO RGDT/FSD VCC ...
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... Revision Identification The Si3035 provides the system designer the ability to determine the revision of the Si3021 and/or the Si3012. Register 11 identifies the revision of the Si3021 with 4 bits named REVA. Register 13 identifies the revision of the Si3012 with 4 bits named REVB. Table 19 shows the values for the various revisions. ...
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... DSP can read several status bits. The bit of highest importance is the frame detect bit (FDT, Register 12, bit 6). This bit indicates that the DSP-side (Si3021) and line-side (Si3012) devices are communicating. During normal operation, the FDT bit can be checked before reading any bits that indicate information about the line side ...
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Control Registers Any register not listed here is reserved and should not be written. Register Name Bit 7 1 Control Control 2 3 Control 3 4 Control 4 5 DAA Control 1 6 ...
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Register 1. Control 1 Bit Name SR Type R/W Reset settings = 0000_0000 Bit Name 7 SR Software Reset Enables chip for normal operation Sets all registers to their reset value. 6:2 ...
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Register 3. Control 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 Reserved Read returns zero. Register 4. Control 4 Bit Name Type Reset settings = ...
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Register 5. DAA Control 1 Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 OPOL Off-Hook Polarity Off-hook pin is active low Off-hook pin is active high. ...
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... Normal operation. Program the clock generator before clearing this bit Places the Si3012 in power down or reset state. 3 PDN Power Down Normal operation Powers down the Si3021. A pulse on RESET is required to restore normal operation. 2 Reserved Read returns zero. Register 7. PLL1 Divide N1 Bit D7 D6 ...
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Register 8. PLL1 Multiply M1 Bit Name M1[7:0] Type R/W Reset settings = 0000_0000 (serial mode 0, 1) Reset settings = 0001_0011 (serial mode 2) Bit Name 7:0 M1[7:0] M1 Multiplier. Contains the (value – 1) ...
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... Name 7 CLE Communications (ISOcap Link) Error ISOcap communication link between the Si3021 and the Si3012 is operating correctly Indicates a communication problem between the Si3021 and the Si3012. A write reset is required to clear this bit. 6 FDT Frame Detect Indicates ISOcap link has not established frame lock. ...
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Register 13. Transmit and Receive Gain Bit Name CBID REVB[3:0] Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 CBID Chip B ID Indicates the line side is domestic ...
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Register 14. Daisy-Chain Control Bit Name NSLV2 NSLV1 NSLV0 SSEL1 SSEL0 Type R/W R/W R/W Reset settings = 0000_0010 (serial mode 0, 1) Reset settings = 0011_1111 (serial mode 2) Bit Name 7:5 ...
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Register 15.TX/RX Gain Control Bit Name TXM ATX2 ATX1 Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 TXM Transmit Mute Transmit signal is not muted Mutes the transmit signal. 6:4 ...
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Register 16. IIR Filter Control Bit Name IIRE Type R/W R/W R/W R/W Reset settings = 0000_1000 Bit Name 7:5 Reserved Read returns zero (must always be written with ...
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A —U L1 950 Although designs using the Si3035 comply with UL1950 3rd Edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. Figure 31 shows two ...
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... Serial Port Bit Clock Output. Controls the serial data on SDO and latches the data on SDI. Digital Supply Voltage. Provides the digital supply voltage to the Si3021, nominally either 3.3 V. Serial Port Data Output. Serial communication data that is provided by the Si3021 to the modem/DSP. ...
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... Ground. Connects to the system digital ground. Analog Supply Voltage. Provides the analog supply voltage for the Si3021, nominally 5 V. This supply is typically generated internally with an on-chip charge pump set through a control register. Mode Select 0 Input. The first of two mode select pins that is used to select the operation of the serial port/DSP interface ...
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Pin Descriptions: Si3012 (SOIC or TSSOP) Pin Name Pin # Test Input A. 1 TSTA Allows access to test modes which are reserved for factory use. This pin has an internal pull-up and should be left ...
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Table 22. Si3012 Pin Descriptions (Continued) (SOIC or TSSOP) Pin Name Pin # Hybrid Node Output. 11 HYBD Balancing capacitor connection used for JATE out-of-band noise support. DC Termination. 12 DCT Provides DC termination to the telephone network. External Resistor. ...
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... Line Digital (SOIC) (SOIC) (TSSOP) Si3021-KS Si3014-KS Si3021-KT Si3021-KS Si3012-KS Si3021-KT Si3024-KS Si3012-KS Si3024-KT Si3024-KS Si3014-KS Si3024-KT Si3021-KS Si3015-KS Si3021-BS Si3015-BS Si3025-KS Si3012-KS Si3025-KS Si3014-KS Rev. 1.2 Line Temperature (TSSOP) Si3014-KT 0°C to 70°C Si3012-KT 0°C to 70°C Si3012-KT 0°C to 70°C Si3014-KT 0° ...
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... SOIC Outline Figure 32 illustrates the package details for the Si3021 and Si3012. Table 24 lists the values for the dimensions shown in the illustration. Figure 32. 16-pin Small Outline Plastic Package (SOIC) Table 24. Package Diagram Dimensions Controlling Dimension: mm Symbol ...
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... TSSOP Outline Figure 33 illustrates the package details for the Si3021 and Si3014. Table 25 lists the values for the dimensions shown in the illustration Figure 33. 16-pin Thin Small Shrink Outline Package (TSSOP) Table 25. Package Diagram Dimensions ...
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Data Sheet Changes from Version 1.0 to Version 1.1 Typical Application Circuit was updated. C24, C25 value changed from 470 pF to 1000 pF and C31, C32 were added in Table 13. The tolerance was also changed from ...
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Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in ...