FM24C256-S RAMTR, FM24C256-S Datasheet
FM24C256-S
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FM24C256-S Summary of contents
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... product offers A2 VSS Pin Names A0-A2 SDA SCL WP VSS VDD Ordering Information FM24C256-S 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058 VDD SCL SDA Function Device Select Address Serial Data/address Serial Clock ...
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... The SCL input also incorporates a schmit trigger input for noise immunity. Write Protect. When tied to VDD, the entire array will be write- protected. When WP is connected to ground, all addresses may be written. This pin is pulled down internally. Supply Voltage. 5V FM24C256 4,096 x 64 FRAM Array 8 Data Latch 2/12 ...
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... This is explained in more detail in the interface section below. Users expect several obvious system benefits from the FM24C256 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example ...
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... If the receiver acknowledges the last byte, this will cause the FM24C256 to attempt to drive the bus on the next clock while the master is sending a new command such as stop. ...
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... After the address information has been transmitted, data transfer between the bus master and the FM24C256 can begin. For a read operation the FM24C256 will place 8 data bits on the bus then wait for an acknowledge from the master. If the acknowledge occurs, the FM24C256 will transfer the next sequential byte ...
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... Each time the bus master acknowledges a byte, this indicates that the FM24C256 should read out the next sequential byte. There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24C256 10 April 2001 Address & Data X 0 ...
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... Each access causes a cycle for an entire row. Therefore, data locations targeted for substantially differing numbers of cycles should not be located within the same row. In the FM24C256, a row is 64 bits wide. Each 8 bytes in the address marks the beginning of a new row. ...
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... When time to market is critical, FRAM can eliminate this simple obstacle. As soon as a write is issued to the FM24C256 effectively done -- no waiting. 5. RF/ID. In the area of contactless memory, FRAM provides an ideal solution. Since RF/ID memory is powered field, the long programming time and high current consumption needed to write EEPROM is unattractive ...
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... VIH. This impedance is characterized and not tested. 10 April 2001 Ratings - -1.0V to +7. 300 C Min Typ Max 4.5 5.0 5.5 115 150 400 500 1 1 -0.3 VDD x 0.3 VDD x 0.7 VDD + 0.5 0 VDD x .05 FM24C256 Units Notes 1 9/12 ...
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... Max Min 0 100 0 4.7 1.3 4.0 0.6 3 4.7 1.3 4.0 0.6 4.7 0 250 100 1000 300 4.0 0 Max Units Notes VDD * 0.1 to VDD * 0 VDD*0.5 FM24C256 Max Min Max Units Notes 400 0 1000 kHz 0.6 s 0.4 s 0.9 0.55 s 0.5 s 0. 100 ns 300 300 ns 1 300 100 ...
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... Data retention is specified The relationship between retention, temperature, and the associated reliability level is characterized separately. 10 April 2001 t HIGH 1/fSCL t AA Stop Start t HD:DAT t t SU:DAT HD:STA Stop Start Units Notes Years 1 FM24C256 LOW t HD:DAT t SU Acknowledge t AA Acknowledge 11/12 ...
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... B mm 0.33 in. 0.013 C mm 0.23 in. 0.0091 D mm 12.6 in. 0.4961 E mm 7.40 in. 0.2914 10.00 in. 0.394 h mm 0.25 in. 0.010 L mm .40 in. 0.016 0 10 April 2001 . .004 in. Nom. Max 2.65 0.1043 0.30 0.0118 0.51 0.020 0.32 0.0125 13.0 0.5118 7.60 0.2992 1.27 BSC 0.050 BSC 10.65 0.419 0.75 0.029 1.27 0.050 8 FM24C256 12/12 ...