RTL8139DL ETC-unknow, RTL8139DL Datasheet
RTL8139DL
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RTL8139DL Summary of contents
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... RTL8139D RTL8139DL RTL8139D-LF RTL8139DL-LF RTL8139D-GR RTL8139DL-GR SINGLE-CHIP MULTI-FUNCTION 10/100Mbps ETHERNET CONTROLLER WITH POWER MANAGEMENT DATASHEET Rev. 1.2 08 Aug 2005 Track ID: JATR-1076-21 ...
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... Realtek representative for additional information that may help in the development process. REVISION HISTORY Revision Release Date 1.2 2005/08/08 Single Chip Multifunction 10/100 Ethernet Controller w/Power Management Summary Added section 13 Ordering Information, on page 61. Added lead (Pb)-free and version package identification information on page 2 and page 3. RTL8139DL Datasheet ii Track ID: JATR-1076-21 Rev. 1.2 ...
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... EGISTER R 3.............................................................................22 EGISTER R 4.............................................................................23 EGISTER S R .............................................................................24 ELECT EGISTER ID .................................................................................................................. (TSAD ESCRIPTORS R ........................................................................................25 ONTROL EGISTER R ...........................................................................................26 TATUS EGISTER A R DVERTISEMENT EGISTER INK ARTNER BILITY E R .........................................................................28 XPANSION EGISTER ........................................................................................................28 OUNTER .......................................................................4 ............................................................10 EADER ..............................................24 EGISTER .................................................................26 R .....................................................27 EGISTER iii Track ID: JATR-1076-21 Rev. 1.2 RTL8139DL Datasheet ...
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... R .............................................................................................29 EGISTER R 5 ...............................................................................30 EGISTER EGISTERS M OWER ANAGEMENT S T .....................................................................................34 PACE ABLE S F ..............................................................................36 PACE UNCTIONS P - (RSTB A OWER ON F ...............................................................................41 ANAGEMENT UNCTIONS .........................................................................................................46 ............................................................................................................46 C ...................................................................................46 OMPENSATION M ......................................................................................................46 ONITOR M .................................................................................................47 ODULE ........................................................................................................47 .............................................................................................................47 .............................................................................................................48 ....................................................................................................................48 ................................................................................................................... .............................................................................................52 IMIT ATINGS ..........................................................................................................52 ..........................................................................................................53 ............................................................33 R ................................................33 EGISTERS ) ....................................................40 SSERTED iv Track ID: JATR-1076-21 Rev. 1.2 RTL8139DL Datasheet ...
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... MECHANICAL DIMENSIONS ......................................................................................59 12.1. QFP ......................................................................................................................................59 12.2. LQFP....................................................................................................................................60 13. ORDERING INFORMATION.........................................................................................61 Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139DL Datasheet v Track ID: JATR-1076-21 Rev. 1.2 ...
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... The RTL8139D(L) includes a PCI and Expansion Memory Share Interface (Realtek’s patent pending) for a boot ROM and can be used in diskless workstations, providing maximum network security and ease of management. Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139DL Datasheet 1 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Supports LED pins for various network activity indications Supports loopback capability Half/Full duplex capability Supports Full Duplex Flow Control (IEEE 802.3x) 2.5/3.3V power supply with 5V tolerant I/ 128K byte Boot ROM interface for both EPROM and Flash memory is supported 0.25u CMOS process 2 Track ID: JATR-1076-21 Rev. 1.2 RTL8139DL Datasheet ...
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... Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 1. ‘Green’ package is indicated by a ‘G’ in the location marked ‘T’ in Figure 1. Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139D QFP LLLLLLL TXXXX TAIWAN Figure 1. Pin Assignments (100-Pin QFP) RTL8139DL Datasheet 65 RTSET 64 LWAKE 63 RTT3 62 GND 61 X1 ...
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... RXIN AVDD 71 TXD- 72 TXD+ 73 GND 74 ISOLATEB 75 AVDD LED2 78 IDSEL2 79 LED1 80 LED0 81 INTAB 82 RSTB 83 CLK 84 GNTB 85 REQB 86 AD31 RTL8139DL LQFP 87 AD30 88 GND 89 AD29 90 VDD 91 AD28 92 AD27 93 AD26 94 AD25 95 AD24 96 VDD25 97 VDD 98 CBE3B 99 IDSEL 100 AD23 1 AD22 2 GND 3 AD21 4 AD20 5 AD19 ...
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... FRAMEB is asserted low to indicate the start of a bus transaction. While FRAMEB is asserted, data transfer continues. When FRAMEB is deasserted, the transaction is in the final data phase target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it. RTL8139DL Datasheet Description Description 4 ...
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... RTL8139D(L) asserts both SERRB pin low and bit 14 of Status register in Configuration Space. 17 Stop: Indicates the current target is requesting the master to stop the current transaction. 82 Reset: When RSTB is asserted low, the RTL8139D(L) performs internal system hardware reset. RSTB must be held for a minimum of 120 ns. RTL8139DL Datasheet Description 5 Track ID: JATR-1076-21 Rev. 1.2 ...
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... EEPROM chip select Pin No +3.3V (Digital) 59,70,75 +3.3V (Analog) 51,96 +2.5V (Digital) 58 +2.5V (Analog) Ground 62,66,73,88 Pin No 80,79,77 LED pins LEDS1-0 LED0 LED1 LED2 During power down mode, the LED’s are OFF. RTL8139DL Description Description Description TX/RX TX/RX TX LINK100 LINK10/100 LINK10/100 LINK10 FULL RX 6 Track ID: JATR-1076-21 Rev. 1.2 Datasheet ...
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... CLKRUNB. For the host system S/T/S signal. The host system (central resource) is responsible for maintaining CLKRUNB asserted, and for driving it high to the negated (deasserted) state. 7,40,69,76 Reserved RTL8139DL Description Description nd device will assert this pin low to request the nd device ...
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... Writing any value to this 32-bit register will reset the original timer and begin to count from zero. MPC Missed Packet Counter: Indicates the number of packets discarded due to Rx FIFO overflow 24-bit counter. After s/w reset, MPC is cleared. Only the lower 3 bytes are valid. RTL8139DL Datasheet 8 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Power Management wakeup frame3 (64bit) Wakeup4 Power Management wakeup frame4 (64bit) Wakeup5 Power Management wakeup frame5 (64bit) Wakeup6 Power Management wakeup frame6 (64bit) Wakeup7 Power Management wakeup frame7 (64bit) LSBCRC0 LSB of the mask byte of wakeup frame0 within offset RTL8139DL Datasheet 9 Track ID: JATR-1076-21 Rev. 1.2 ...
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... CRC Error: When set, indicates that a CRC error occurred on the received packet. FAE Frame Alignment Error: When set, indicates that a frame alignment error occurred on this received packet. ROK Receive OK: When set, indicates that a good packet is received. RTL8139DL Datasheet Description 10 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Descriptor Size: The total size in bytes of the data in this descriptor. If the packet length is more than 1792 byte (0700h), the Tx queue will be invalid, i.e. the next descriptor will be written only after the OWN bit of that long packet's descriptor has been set. RTL8139DL Datasheet Description 11 ...
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... After initial power-up, software must insure that the transmitter has completely reset before setting this bit. - Reserved BUFE Buffer Empty: Rx Buffer Empty. There is no packet stored in the Rx buffer ring. RTL8139DL Datasheet Description Description 12 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Transmit (Tx) Error: Indicates that a packet transmission was aborted, due to excessive collisions, according to the TXRR's setting. TOK Transmit (Tx) OK: Indicates that a packet transmission is completed successfully. RER Receive (Rx) Error: Indicates that a packet has either CRC error or RTL8139DL Datasheet Description Description 13 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Other combination 8.4us + 0.4(IFG(1:0)) us 840ns + 40(IFG(1:0 Track ID: JATR-1076-21 Rev. 1.2 RTL8139DL Datasheet ...
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... RTL8139D(L)'s definition. 0000 = no early rx threshold 0010 = 2/16 0100 = 4/16 0110 = 6/16 1000 = 8/16 1010 = 10/16 1100 = 12/16 RTL8139DL Datasheet Description Total retries = 16 + (TXRR * 16) Description 0001 = 1/16 0011 = 3/16 0101 = 5/16 0111 = 7/16 1001 = 9/16 ...
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... WRAP When set to 0: The RTL8139D(L) will transfer the rest of the packet data into the beginning of the Rx buffer if this packet has not been completely moved into the Rx buffer and the transfer has arrived at the end of the Rx buffer. RTL8139DL Datasheet Description 1111 = 15/16 16 ...
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... Accept Broadcast packets: Set accept reject. AM Accept Multicast packets: Set accept reject. APM Accept Physical Match packets: Set accept reject. AAP Accept All Packets: Set accept all packets with a physical destination address reject. RTL8139DL Datasheet Description 17 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Reserved EECS These bits reflect the state of EECS, EESK, EEDI & EEDO pins in auto-load or 93C46 programming mode. EESK EEDI EEDO RTL8139DL Description Operating Mode Normal (RTL8139D(L) network/host communication mode) Auto-load: Entering this mode will RTL8139D(L) load the contents of 93C46 like when the RSTB signal is asserted ...
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... T10 10Mbps Mode: Always 0. PL1, PL0 Select 10Mbps medium type: Always (PL1, PL0) = (1, 0) Select Boot ROM size (Autoloaded from EEPROM) BS2 RTL8139DL Datasheet Description BS1 BS0 Description Boot ROM Boot ROM 1 0 16K Boot ROM ...
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... Let D denote the power management registers in the PCI Configuration space offset from 52H to 57H. Let E denote the Next_Ptr (power management) register in the PCI Configuration space offset 51H. PMEn Description 0 A=B=C=E=0, D not valid 1 A=1, B=50h, C=01h, D valid, E=0 RTL8139DL Datasheet LWACT 0 1 Active low Negative pulse 20 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Transmit Pause Flag: Set, when RTL8139D(L) sends pause packet. Reset, when RTL8139D(L) sends a timer done packet. RXPF Receive Pause Flag: Set, when RTL8139D( backoff state because a pause packet was received. Reset, when pause state is clear. RTL8139DL Datasheet Description Remote TXFCE/LdTXFCE ...
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... The RTL8139D(L), in adequate power state, will assert the PMEB signal to wakeup the operating system when the cable connection is re-established. - Reserved CLKRUN Enable: Set disable CLKRUN Set enable CLKRUN - Reserved FBtBEn Fast Back to Back Enable: Set enable Fast Back to Back. RTL8139DL Datasheet Description 22 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Set to 0: The LWAKE and PMEB are asserted at the same time. - Reserved LWPTN LWAKE pattern: Please refer to LWACT bit in CONFIG1 register. - Reserved PBWakeup Pre-Boot Wakeup: The initial value comes from EEPROM autoload. 1: Pre-Boot Wakeup disabled. (suitable for CardBus and MiniPCI applications) 0: Pre-Boot Wakeup enabled. RTL8139DL Datasheet Description 23 Track ID: JATR-1076-21 Rev. 1.2 ...
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... TUN bit of Descriptor 0 TABT3 TABT bit of Descriptor 3 TABT2 TABT bit of Descriptor 2 TABT1 TABT bit of Descriptor 1 TABT0 TABT bit of Descriptor 0 OWN3 OWN bit of Descriptor 3 OWN2 OWN bit of Descriptor 2 OWN1 OWN bit of Descriptor 1 OWN0 OWN bit of Descriptor 0 RTL8139DL Datasheet Description Description Description 24 Track ID: JATR-1076-21 Rev. 1.2 ...
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... This bit allows the NWay auto-negotiation function to be reset re-start auto-negotiation normal operation. This bit sets the duplex mode normal operation ; 1 = full-duplex. This bit‘s initial value comes from 93C46. If bit12 = 1, read = status write = register value. If bit12 = 0, read = write = register value. Reserved RTL8139DL Datasheet Default/Attribute ...
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... Reserved 1 = flow control is supported by local node flow control is not supported by local mode 100Base-T4 is supported by local node 100Base-T4 not supported by local node 100Base-TX full duplex is supported by local node 100Base-TX full duplex not supported by local node. RTL8139DL Datasheet Default/Attribute ...
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... Link Partner's binary encoded node selector. Currently only CSMA/ CD <00001> is specified. RTL8139DL Datasheet Default/Attribute <00001>, RW ...
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... This 16-bit counter increments by 1 for every disconnect event. It rolls over when becomes full cleared to zero by read command. Description/Usage This 16-bit counter increments by 1 for each false carrier event cleared to zero by read command. RTL8139DL Datasheet Default/Attribute - ...
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... Assertion of this bit forces the disconnect function to be bypassed. Reserved This bit indicates the status of the connection valid connected link detected disconnected link detected. Assertion of this bit configures LED1 pin to indicate connection status. Reserved Bypass Scramble RTL8139DL Datasheet Default/Attribute - ...
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... Link should be established again. LANWake signal enable/disable: 1: Enable LANWake signal. 0: Disable LANWake signal. PME_Status bit: Always sticky/can be reset by PCI RST# and software. 1: The PME_Status bit can be reset by PCI reset or by software. 0: The PME_Status bit can only be reset by software. RTL8139DL Datasheet Description 30 Track ID: JATR-1076-21 Rev. 1.2 ...
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... PHY Parameter 1-U for RTL8139D(L). Operational registers of the RTL8139D(L) are from 78h to 7Bh. Reserved. Do not change this filed without Realtek approval. PHY Parameter 2-U for RTL8139D(L). Operational register of the RTL8139D(L) is 80h. Do not change this filed without Realtek approval. RTL8139DL Description 31 Track ID: JATR-1076-21 Rev. 1.2 Datasheet ...
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... Checksum of the EEPROM content. Reserved. Do not change this filed without Realtek approval. Reserved. Do not change this filed without Realtek approval. PXE ROM code parameter. VPD data filed. Offset 40h is the start address of the VPD data. RTL8139DL Description 32 Track ID: JATR-1076-21 Rev. 1.2 Datasheet ...
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... LinkUp - - LWPME - LWPTN 32 bit Read Write 32 bit Read Write 32 bit Read Write 8 bit Read Write - - LDPS Bit4 Bit3 Bit2 Reserved PMECLK Track ID: JATR-1076-21 Rev. 1.2 RTL8139DL Datasheet Bit1 Bit0 BS1 BS0 - - VPD PMEN VPD PMEN - FUDUP - FUDUP - FBtBEn - - - - LANWa PME_ST ke S Bit1 ...
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... SMID14 SMID13 SMID12 BMAR14 BMAR13 BMAR12 BMAR11 BMAR14 BMAR13 BMAR12 BMAR11 BMAR22 BMAR21 BMAR20 BMAR19 BMAR18 BMAR17 BMAR16 BMAR30 BMAR29 BMAR28 BMAR27 BMAR26 BMAR25 BMAR24 RESERVED RTL8139DL Datasheet Bit3 Bit2 Bit1 BMEN MEMEN - ...
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... VPDADDR VPDADD VPDADD VPDADDR VPDADD VPDADD 14 R13 R12 Data6 Data5 Data4 Data14 Data13 Data12 Data22 Data21 Data20 Data30 Data29 Data28 RESERVED RTL8139DL Datasheet Bit3 Bit2 Bit1 ILR3 ILR2 ILR1 Version Power State ...
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... RTL8139D(L) ignores memory space accesses. 0 IOEN I/O Space Access: When set to 1, the RTL8139D(L) responds to IO space access. When set to 0, the RTL8139D(L) ignores I/O space accesses. Single Chip Multifunction 10/100 Ethernet Controller w/Power Management Description 36 Track ID: JATR-1076-21 Rev. 1.2 RTL8139DL Datasheet ...
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... Specifies, in units of PCI bus clocks, the value of the latency timer of the RTL8139D(L). When the RTL8139D(L) asserts FRAMEB, it enables its latency timer to count. If the RTL8139D(L) deasserts FRAMEB prior to count expiration, the content of the latency timer is ignored. Otherwise, Single Chip Multifunction 10/100 Ethernet Controller w/Power Management Description 37 Track ID: JATR-1076-21 Rev. 1.2 RTL8139DL Datasheet ...
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... BMAR: This register specifies the base memory address for memory accesses to the Rtl8139D(L) operational registers. This register must be initialized prior to accessing any Rtl8139D(L) 's register with memory access. Single Chip Multifunction 10/100 Ethernet Controller w/Power Management Description Description 38 Track ID: JATR-1076-21 Rev. 1.2 RTL8139DL Datasheet ...
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... Specifies how often the RTL8139D(L) needs to gain access to the PCI bus in unit of 1/4 microsecond. This field will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h. Single Chip Multifunction 10/100 Ethernet Controller w/Power Management Description 39 Track ID: JATR-1076-21 Rev. 1.2 RTL8139DL Datasheet ...
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... Ptr4 Ptr3 Ptr2 40 Track ID: JATR-1076-21 Rev. 1.2 RTL8139DL Datasheet Bit1 Bit0 IOEN SERREN DPD LTR0 ...
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... Tx FIFO from the last break. The packet that was not transmitted completely last time is transmitted again. Single Chip Multifunction 10/100 Ethernet Controller w/Power Management Bit7 Bit6 Bit5 RESERVED(ALL 0) RTL8139DL Bit4 Bit3 Bit2 Bit1 Track ID: JATR-1076-21 Rev. 1.2 ...
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... The PMEn bit (CONFIG1#0) is set The 8-bit CRC (or 16-bit CRC) of the received Wakeup Frame matches with the 8-bit CRC 16-bit CRC) of the sample Wakeup Frame pattern received from the local machine’s OS. Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139DL Datasheet 42 Track ID: JATR-1076-21 Rev. 1.2 * (or ...
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... There is no hardware enforced delays at RTL8139D(L)’s power state. When in ACPI mode, the RTL8139D(L) does not support PME from D0 (owing to the setting of PMC register. This setting comes from EEPROM). Single Chip Multifunction 10/100 Ethernet Controller w/Power Management of the received Wakeup Frame matches with the last masked byte RTL8139DL Datasheet ** 43 Track ID: JATR-1076-21 Rev. 1.2 of the ...
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... Write the flag bit to a zero at the same time the VPD address is written). When the flag bit is set to one by the RTL8139D(L), the VPD data (all 4 bytes) has been transferred from 93C46 to the VPD data register. Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139DL Datasheet 44 ...
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... Receive low pass filter TD+ Parrallel to Serial Variable Current Baseline wander Correction 3 Level MLT-3 Comparator to NRZI ck Slave PLL data Control Voltage RTL8139DL LED Driver Transmit/ Receive MII Logic Interface Interface RXD Descrambler RXC 25M TXD TXC 25M Link pulse shaping TXO+ 3 Level Driver ...
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... This function allows for a quick and simple verification of the line quality in that any significant deviation from an expected register value (based on a known cable length) would indicate that the signal quality has deviated from the expected nominal case. Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139DL Datasheet 46 Track ID: JATR-1076-21 Rev. 1.2 ...
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... If the RTL8139D(L) is not in the full-duplex mode, a collision event occurs when the receive input is not idle while the RTL8139D(L) transmits. If the collision was detected during the preamble transmission, the jam pattern is transmitted after completing the preamble (including the JK symbol pair). Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139DL Datasheet 47 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Note: The PAUSE operation cannot be used to inhibit transmission of MAC Control frames (e.g. PAUSE packet). The N-way flow control capability can be disabled, please refer to Section 6, EEPROM (93C46) Contents for a detailed description. Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139DL Datasheet 48 Track ID: JATR-1076-21 Rev. 1.2 ...
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... The Link Monitor senses the link integrity station is down. 9.11.2. LED_RX In 10/100 Mbps mode, the LED function is the same as the RTL8139C(L). Single Chip Multifunction 10/100 Ethernet Controller w/Power Management Power On LED = Low No Receiving Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( Track ID: JATR-1076-21 Rev. 1.2 RTL8139DL Datasheet ...
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... Single Chip Multifunction 10/100 Ethernet Controller w/Power Management Power On LED = Low No Transmitting Packet Yes LED = High for (100 +- 10) ms LED = Low for ( Power On LED = Low Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( RTL8139DL Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...
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... Application Diagram RJ45 Magetics Single Chip Multifunction 10/100 Ethernet Controller w/Power Management LED EEPROM RTL8102L CS/OE BootROM Auxiliary Power PCI INTERFACE RTL8139DL Datasheet REQB GNTB nd 2 PCI Device IDSEL INTA 51 Track ID: JATR-1076-21 Rev. 1.2 ...
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... V IN -1.0 GND V OUT -10 GND I OUT= 0mA, Conditions Minimum I OH= -8mA 0.9 * Vdd25 I OL= 8mA 0.5 * Vdd25 -0.5 V IN= V dd25 or -1.0 GND V OUT= V dd25 or -10 GND I OUT= 0mA, 52 RTL8139DL Datasheet Units °C °C Maximum Units Vcc V 0.1 * Vcc V Vcc+0.5 V 0.3 * Vcc V 1 330 mA Maximum ...
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... AC Characteristics 11.3.1. PCI Bus Operation Timing Target Read Target Write Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139DL Datasheet 53 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Configuration Read Configuration Write Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139DL Datasheet 54 Track ID: JATR-1076-21 Rev. 1.2 ...
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... BUS Arbitration Memory Read Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139DL Datasheet 55 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Memory Write Target Initiated Termination - Retry Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139DL Datasheet 56 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Target Initiated Termination - Disconnect Target Initiated Termination - Abort Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139DL Datasheet 57 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Master Initiated Termination – Abort Parity Operation - one example Single Chip Multifunction 10/100 Ethernet Controller w/Power Management RTL8139DL Datasheet 58 Track ID: JATR-1076-21 Rev. 1.2 ...
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... Millimeter 3.00 0.51 0.91 4.General appearance spec. should be based on final visual 2.85 3.10 inspection spec. 0.30 0.42 0.26 0.15 TITLE : 100L QFP ( 14x20 mm**2 ) FOOTPRINT 4.8 mm 0.65 0.80 APPROVE 1.20 1.40 2.40 2.65 CHECK - - 0.10 0° - 12° PACKAGE OUTLINE DRAWING LEADFRAME MATERIAL: DWG NO. REV NO. SCALE Ricardo Chen DATE SHT NO REALTEK SEMICONDUCTOR CORP. 59 Track ID: JATR-1076-21 Rev. 1.2 RTL8139DL Datasheet ...
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... REF 0º 3.5º 9º 0º CHECK 12ºTYP 12ºTYP REALTEK SEMICONDUCTOR CORP. and E do not include mold protrusion are maximum plastic body size dimensions TITLE: 100LD LQFP ( 14x14x1.4mm) LEADFRAME MATERIAL: DOC. NO. VERSION 1 PAGE OF DWG NO. LQ100 - P1 DATE 60 Track ID: JATR-1076-21 Rev. 1.2 RTL8139DL Datasheet ...
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... Single Chip Multifunction 10/100 Ethernet Controller w/Power Management Table 1. Ordering Information Package QFP-100 LQFP-100 RTL8139D with Lead (Pb)-Free package RTL8139DL with Lead (Pb)-Free package RTL8139D with ‘Green’ package RTL8139DL with ‘Green’ package RTL8139DL Datasheet Status 61 Track ID: JATR-1076-21 Rev. 1.2 ...