QL12X16B-2PF100C QULOG, QL12X16B-2PF100C Datasheet

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QL12X16B-2PF100C

Manufacturer Part Number
QL12X16B-2PF100C
Description
Very-high-speed CMOS FPGA, pASIC1 family.
Manufacturer
QULOG
Datasheet
usable ASIC gates,
192 Logic Cells
Block Diagram
HIGHLIGHTS
88 I/O pins
QL12x16B
…2,000
pASIC
Low-Power, High-Output Drive – Standby current typically 2
mA. A 16-bit counter operating at 100 MHz consumes less than 50
mA. Minimum IOL of 12 mA and IOH of 8 mA
Low-Cost, Easy-to-Use Design Tools
simulated using QuickLogic's new QuickWorks
environment, or with third-party CAE tools including Viewlogic,
Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place
and route on PC and workstation platforms using QuickLogic
software.
= Up to 80 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells
Very High Speed – ViaLink
antifuse technology, allows counter speeds over 150 MHz and logic
cell delays of under 2 ns.
High Usable Density
provides 2,000 usable ASIC gates (4,000 PLD gates) in 68-pin and
84-pin PLCC, 84-pin CPGA and 100-pin TQFP packages.
4-13
Very-High-Speed CMOS FPGA
A 12-by-16 array of 192 logic cells
metal-to-metal programmable–via
pASIC
Designs entered and
QL12X16B
®
1 Family
development
Rev C
4

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QL12X16B-2PF100C Summary of contents

Page 1

... High Usable Density – A 12-by-16 array of 192 logic cells provides 2,000 usable ASIC gates (4,000 PLD gates) in 68-pin and 84-pin PLCC, 84-pin CPGA and 100-pin TQFP packages. 4-13 QL12X16B ® pASIC 1 Family Rev C metal-to-metal programmable–via – Designs entered and ...

Page 2

... PRODUCT The QL12x16B is a member of the pASIC 1 Family of very-high-speed SUMMARY CMOS user-programmable ASIC devices. The 192 logic cell field- programmable gate array (FPGA) offers 2,000 usable ASIC gates (4,000 usable PLD gates) of high-performance general-purpose logic in a wide variety of package configurations. Low-impedance, provides nonvolatile custom logic capable of operating above 150 MHz ...

Page 3

... QL12x16B Pins identified I/SCLK, SM, SO and SI are used during scan path testing operation. Pinout Diagram 68-pin PLCC Pinout Diagram 84-pin PLCC 4-15 4 ...

Page 4

... I/(SI I/CLK I/(SO) VCC J7 VCC L10 L11 IO 4-16 QL12x16B PIN FUNC K10 IO J10 IO K11 IO J11 IO H10 IO H11 IO G11 IO G9 GND G10 IO F11 IO F10 E11 IO E9 VCC E10 IO D11 IO D10 IO C11 IO ...

Page 5

... QL12x16B Pinout Diagram 100-pin TQFP 4-17 4 ...

Page 6

... Industrial Min Max Min Max 4.5 5.5 4.5 5.5 -55 -40 85 125 0.4 2.75 0.39 1.82 0.4 1.67 0.39 1.56 0.4 1.43 0.4 1.35 Conditions IOH = -4 mA IOH = -8 mA IOH = -10 A IOL = 12 mA* IOL = VCC or GND VI = VCC or GND VO = GND VO = VCC VI, VIO = VCC or GND 4-18 QL12x16B Commercial Unit Min Max 4.75 5. 0.46 2.55 0.46 1.55 0.46 1.33 0.46 1.25 Min Max Unit 2.0 V 0.8 V 3.7 V 2.4 V VCC-0.1 V 0.4 V 0.1 V ...

Page 7

... QL12x16B AC CHARACTERISTICS at VCC = 5V 25° 1.00) Logic Cell Symbol tPD Combinatorial Delay [5] tSU Setup Time [5] tH Hold Time tCLK Clock to Q Delay tCWHI Clock High Time tCWLO Clock Low Time tSET Set Delay tRESET Reset Delay tSW Set Width tRW Reset Width ...

Page 8

... ORDERING INFORMATION pASIC device part number B = 0.65 micron CMOS Clock Drivers Wired Together 12x16B - 1 PF100 C QuickLogic pASIC device prefix Speed Grade X = quick 0 = fast 1 = faster 2 = fastest 4-20 QL12x16B Propagation Delays (ns) [4] Fanout 4.5 5.4 3.9 5.6 4.5 5.3 4.6 4.7 5.6 4.0 5.8 4.6 5.5 4.8 Operating Range C = Commercial I = Industrial ...

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