GS9020 ETC-unknow, GS9020 Datasheet
GS9020
Available stocks
Related parts for GS9020
GS9020 Summary of contents
Page 1
... Receiver, thus providing a complete, high performance, digital video input processor with EDH, digital sync signal generation, and other system features. The GS9020 also includes a parallel to serial converter and NRZI scrambler to provide re-serialized, EDH compliant data output. The EDH core implements EDH insertion and extraction according to SMPTE RP-165 ...
Page 2
ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Input Voltage Range (any input) Operating Temperature Range Storage Temperature Lead Temperature (soldering, 10 sec) DC ELECTRICAL CHARCTERISTICS 70°C unless otherwise shown PARAMETER SYMBOL ...
Page 3
... The serial clock rising edge should occur at the centre of the data period for optimum performance. (See Figure 1) 2. Since the GS9020 does not have a parallel clock input not possible to define timing details relative to it. Instead the GS9020 has a parallel clock output and all timing information is relative to PCLKOUT. The flag port pins (FL[4:0], F_R/W, S[1:0]) are the only inputs where the timing details are important ...
Page 4
... When LOW, the parallel port is configured as an input (write mode). In I²C mode, this pin must be set HIGH. 521 - GS9020 TOP VIEW DESCRIPTION ...
Page 5
... When LOW, the parallel port is used for data input or output. In I²C mode, this pin must be set LOW. Parallel port chip select. When CS is LOW and R/W is HIGH, the GS9020 drives the address/ data bus. When CS is LOW and R/W is LOW, the user should drive the address/data bus. ...
Page 6
PIN DESCRIPTIONS NUMBER SYMBOL TYPE 78 CLIP_TRS I Clip and TRS correction control. When HIGH, the TRS Blanking, ITU-R-601 clipping and TRS insertion features are enabled. 79 TRS_ERR O TRS error indication. When HIGH, indicates a TRS error in the ...
Page 7
... The internal pullup resistors allow the GS9020 to be easily interfaced to the GS9025 as shown in Figure 5 and Figure 17. An external diode is required to offset the input signals to the input range of the GS9020. For maximum signal integrity the GS9025 and GS9020 should be placed as close together as possible. ...
Page 8
Automatic Standard Detection PIN LOGIC OPR STD[3:0] The device automatically detects the incoming video standard. The detected standard is encoded on the STD[3:0] pins and the HOSTIF read table bits as shown in Table 1 and Table 3. TABLE ...
Page 9
... FLYWDIS is available as an input pin and as a bit in the HOSTIF write table. The SWITCHFLYW control signal is used in applications where the data input to the GS9020 is switched between two synchronous signals. In this case, the two signals may be slightly misaligned and would normally require the flywheel to completely re-synchronize ...
Page 10
... EDH packet. The OUTGOING ERROR FLAGS represent the EDH error flags present in the outgoing EDH packet (after modification by the GS9020). Please note that the EDH flags can also be accessed using the flag port as described later. The INCOMING and OUTGOING ERROR FLAGS, the incoming Validity bits (FFV and APV), and the EDH_CHKSM bit can be made " ...
Page 11
... HIGH, the GS9020 overwrites the reserved words in the OUTGOING EDH packet with those specified in the HOSTIF write table. If RO_CTRL is LOW, the GS9020 does not alter the reserved words. RO_CTRL is a control bit in the HOSTIF write table. The reserved words of the INCOMING EDH packet are also available via the HOSTIF read table ...
Page 12
... PIN ANC_CHKSM ANC_DATA EDH_CHKSM The ANC_DATA signal is set HIGH when an ancillary data packet is exiting the GS9020. This pin is asserted from the start of the first header word through to the end of the checksum word of the ANC packet, inclusive, as shown in If the Figure 10. ...
Page 13
... When the F_R/W pin is LOW, the flag port is in write mode and the FL[4:0] pins are configured as inputs. After writing to the flag port, the GS9020 inserts the written flags into the next outgoing EDH packet. Note that external flag overwriting via the flag port takes precedence over HOSTIF overwriting but the flag port writing only affects the next outgoing EDH packet ...
Page 14
... The output EDH chip updates the CRC values to correctly reflect the newly modified data. To prevent the output EDH chip from indicating erroneous CRC errors on each field, the GS9020 has two special modes of operation, CRC_MODE and FLAG_MAP mode. 3.11.1 CRC_MODE ...
Page 15
... F_R/W pin must be asserted HIGH (set F_R/W at least one cycle ahead of FLAG_MAP). After a delay of t FL[4:0] and S[1:0] pins of the FLAG PORT become outputs and can be connected to the chip which you wish the GS9020 to write the FLAG data to. In this mode the GS9020 automatically increments the ...
Page 16
... TRS_INSERT bit of the HOSTIF write table. Note that for proper TRS insertion, the incoming standard must be detected and the flywheel synchronized. That is, the GS9020 does NOT provide proper TRS insertion for unformatted video data (video without TRS words). In the case where the input signal disappears, TRSs will continue to be inserted based on the last detected ...
Page 17
... ANC headers are remapped to 3FF in the output data stream. For example bit data is input to the device, the ANC header of 00, FF, FF will appear as 000, 3FC, 3FC and will be remapped to 000, 3FF, 3FF by the GS9020. 5.0 HOST INTERFACE TABLES PIN HOSTIF_MODE ...
Page 18
... AC timing tables, are relative to this edge HOST BIT and must be met (see Figure 14a) C) The GS9020 drives the P[7:0] bus when the R/W pin is HIGH and the CS pin is LOW. At all other times, the P[7:0] port high impedance state. The host interface enable and disable times are shown in Figure 14b and are specified in the AC timing information ...
Page 19
... Figure 16a illustrates the reset circuitry. The internal power-on reset circuit of the GS9020 is sensitive to the rise time of the power supply, hence an external power on reset chip or board level reset line is strongly recommended. ...
Page 20
521 - ...
Page 21
21 521 - ...
Page 22
... OD Fig. 3 Output Delay & Hold Times (Synchronous Outputs SDO SDO GS9025 SCO SCO Fig. 5 Interfacing the GS9020 to the GS9025 GS9025 SDO SDO SCO SCO 521 - SYNCHRONOUS INPUTS PCLKOUT Fig. 2 Input Setup & Hold Times (Synchronous Inputs SDI ...
Page 23
OS OH PCLKOUT 3FF DOUT [9:0] 000 F [2: Fig. 8a FVH Timing for Component Video PCLKOUT DOUT [9:0] 3FF F [2:0] H Fig and H Timing for Composite Video ...
Page 24
PCLKOUT DOUT[9:0] FIFO_RESET Fig. 9c FIFO_RESET Pulse Timing for Composite Signals (FIFOE PCLKOUT DOUT[9:0] 000 ANC_DATA PCLKOUT DOUT[9:0] 3CF ANC_DATA SDI/SDI EDH DOUT[9:0] INTERRUPT TRANSITION POINT UNKNOWN 521 - 3FF 000 000 000 ...
Page 25
... Fig. 12b Flag Port Disable Time PCLKOUT X F_R/W FLAGMAP FL[4: S[1: FEN Fig. 12d Flag Port Timing in FLAG MAP MODE GS9020 or GS9021 CRC_MODE = 0 R (GS9021) Fig. 13a Example of CRC_MODE Implementation READ CYCLE ANC ...
Page 26
... Fig. 13b Example of FLAG_MAP Mode Implementation P [7:0] A/D R/W CS Fig. 14a HOSTIF Parallel Port Input Setup & Hold Times P[7:0] R/W CS Fig. 14b HOSTIF Parallel Port Output Enable & Disable Times 521 - PROCESSING CORRUPTS EDH PACKET FL [4:0] S [1: HEN GS9020 DRIVING 26 GS9021 FLAG MAP = 0 F_R HDIS ...
Page 27
... READ CYCLE DATA IN ADDRESS DATA FIELD VALID TIME TO READ/WRITE 2 LINES EDH INFORMATION TO/FROM GS9020 = 25µ INTERNAL Manual RESET Reset SIGNAL 1uF Switch (Optional) Fig. 16b Acceptable external reset circuit when a master reset is 27 DATA t 4 FIELD 2 ...
Page 28
VBLANKS/L TRS_ERROR ANC_DATA 521 - FLAG_MAP 66 GND VDD S 69 SDO 70 SDO 71 GND S 72 VBLANKS/L 73 BYPASS_EDH 74 SDOMODE ...
Page 29
FLAG_MAP FLAG_MAP FLAG_MAP FLAG_MAP 66 66 GND GND 67 67 ...
Page 30
PACKAGE DIMENSIONS ±0.20 16.00 ±0.10 14. ±0.08 0.65 BSC 0.30 CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right ...