IP175A ETC-unknow, IP175A Datasheet
IP175A
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IP175A Summary of contents
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... Port 10/100 Ethernet Integrated Switch Features IP175A PCB compatible (pins compatible) Built in 6 MAC and 5 PHY Each port can be configured to be 10Base-T, 100Base-TX 2k MAC address 384k bits packet buffer memory Support auto-polarity for 10Mbps Filter/ forward reserved address option Broadcast storm protection ...
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... Table Of Contents Features................................................................................................................................................... 1 General Description................................................................................................................................. 1 Table Of Contents.................................................................................................................................... 2 Revision History....................................................................................................................................... 4 Comparison Table of IP175A & IP175C/IP175CH................................................................................... 6 Pin diagram (IP175C) .............................................................................................................................. 7 Pin diagram (IP175CH) ........................................................................................................................... 8 1 Pin description................................................................................................................................ 12 2 Functional Description.................................................................................................................... 34 2.1 Flow control........................................................................................................................ 34 2.2 Broadcast storm protection ................................................................................................ 34 2.3 Port locking (Port security)................................................................................................. 34 2.4 Port base VLAN ................................................................................................................. 34 2.5 Tag VLAN / Tag and un-tag function .................................................................................. 35 2 ...
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EEPROM Timing................................................................................................. 109 3.4 Thermal Data ................................................................................................................... 109 4 Order Information ..........................................................................................................................110 5 Package Detail .............................................................................................................................. 111 Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF 3/111 Data Sheet Mar 09, 2007 IP175C/IP175CH-DS-R14 ...
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... RMII clock output pin changed. 2-3. Pin 116: CLK_SEL Î REG_HIGH IP175C-DS-R02 1. Modify RMII1 Pin description. 2. MII Register not compatible to IP175A. 3. Add comparison table of IP175A & IP175C. IP175C-DS-R03 1. Update page 28 Pin description Add page 99~105 3. Remove POA 4. Remove MII registers PHY 5 and PHY 6 IP175C-DS-R04 1 ...
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Revision History Revision # IP175C-DS-R12 1. Change to EEPROM register 14~18 or MII register 19~21 on page 32 2. Add SERIAL_LED_MODE to Pin diagram on page 6 3. Add pin 112 description for SERIAL_LED_MODE on page 27 4. Add PHY_31_REG_5[1] ...
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... Comparison Table of IP175A & IP175C/IP175CH Item/Part Number Pin Assignment Process Package Type Major Block MAC Address AUTO-MDI-MDIX 10M/100M Copper (10BT, 100BaseTx) 100M Fiber (100BaseFX) Max Frame Size 4+1+1: 4Tx+Two MII I/F (RMII I/F) 4+ 3MII 5+1: 5Tx+1 MII I/F SMI I/F(MDC/MDIO) CTRL PHY reg. SNI I/F EEPROM I/F (24C01A) Flow Control-802 ...
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Pin diagram (IP175C ...
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Pin diagram (IP175CH ...
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When pin 74 P4EXT is pulled low, all MII/RMII ports are disabled, and IP175C/IP175CH works as a 5-port switch. MAC5 is not used in this application. switch engine IP175C MAC5 ..... MAC0 MAC4 PHY PHY PHY 0 ...
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Router application using one MII/RMII port (can be configured to 4LAN+1WAN, 3LAN+2WAN, 2LAN+3WAN or 1LAN+4WAN) p4ext mii1_dis mii2_en Switch Engine MAC 0 MAC 1 MAC 2 MAC 3 PHY 0 PHY 1 PHY 2 PHY 3 TP ...
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Router application using two-MII/RMII ports (another option) p4ext mii1_dis mii2_en Switch Engine MAC 0 MAC 1 MAC 2 MAC 3 PHY 0 PHY 1 PHY 2 PHY 3 TP Router application using three-MII/RMII ports p4ext mii1_dis mii2_en ...
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Pin description Type Description I Input pin O Output pin IPL Input pin with internal pull low 50M ohm IPH Input pin with internal pull high 50M ohm Pin No. Label Analog 120 REG_OUT 116 REG_HIGH Copyright © 2004, ...
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Pin description (continued) Pin No. Label LED pins used as initial setting (the setting is latched at the end of reset) 102 BF_STM_EN 101 LINK_Q 100 X_EN Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Type IPL1 Broadcast storm ...
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Pin description (continued) Pin No. Label MII pins used as initial setting (the setting is latched at the end of reset) 69 FILTER_RSV _DA 66 LONG_PKT 65 AGING 64 P4_HIGH 63 COS_EN Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH ...
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Pin description (continued) Pin No. Label Initial setting 36 LOW_10M_EN Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Type IPL 10M low power mode enable 1: 10M low power mode, the trasmit amplitude is depressed in 10M mode for ...
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Pin description (continued) Pin No. Label External MII port setting (the setting is latched at the end of reset) 74 P4EXT 53 RMII_EN 67 MAC_X_EN 96 MII0_MAC_MOD 54 MII1_PHY_MOD IPH/O External MII1 source port selection (SDA) 111 MII2_MAC_MOD 113 MII2_EN ...
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Pin description (continued) Pin No. Label External MII port setting 75 P4MII_SNI 51 MII1_DIS Configuration summary mode p4ext mii1_dis MII/RMII0 MII/ PHY mode 1 X MII/ MAC mode 1 X RMII 1 X SNI/ PHY mode 1 X SNI/ MAC ...
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Pin description (continued) Pin No. Label External MII0 interface (PHY mode, MII0_MAC_MOD=0, P4MII_SNI=0) 89 MII0_RXCLK 81 MII0_TXCLK 80, 79, TXD0_0, TXD0_1, 78, 77 TXD0_2, TXD0_3 76 TXEN0 90 COL0 84 RXDV0 88, 87, RXD0_0, RXD0_1, 86, 85 RXD0_2, RXD0_3 Copyright ...
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Pin description (continued) Pin No. Label External MII0 interface (MAC mode, MII0_MAC_MOD=1, P4MII_SNI=0) 81 MII0_TXCLK 80, 79, TXD0_0, TXD0_1, 78, 77 TXD0_2, TXD0_3 76 TXEN0 90 COL0 84 RXDV0 88, 87, RXD0_0, RXD0_1, 86, 85 RXD0_2, RXD0_3 89 MII0_RXCLK Copyright ...
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Pin description (continued) Pin No. Label External MII1 interface (PHY mode, MII1_PHY_MOD=1, P4EXT=1) 62 MII1_TXCLK 61, 60, TXD1_0, TXD1_1, 59, 58 TXD1_2, TXD1_3 57 TXEN1 69 COL1 63 RXDV1 67, 66, RXD1_0, RXD1_1, 65, 64 RXD1_2, RXD1_3 68 MII1_RXCLK Copyright ...
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Pin description (continued) Pin No. Label External MII2 interface (PHY mode, MII2_MAC_MOD=0, MII2_EN=1) 109 MII2_RXCLK 103 MII2_TXCLK 102, 101, TXD2_0, TXD2_1, 100, 97 TXD2_2, TXD2_3 96 TXEN2 110 COL2 104 RXDV2 108, 107, RXD2_0, RXD2_1, 106, 105 RXD2_2, RXD2_3 Copyright ...
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Pin description (continued) Pin No. Label External MII2 interface (MAC mode, MII2_MAC_MOD=1, MII2_EN=1) 103 MII2_TXCLK 102, 101, TXD2_0, TXD2_1, 100, 97 TXD2_2, TXD2_3 96 TXEN2 110 COL2 104 RXDV2 108, 107, RXD2_0, RXD2_1, 106, 105 RXD2_2, RXD2_3 109 MII2_RXCLK Copyright ...
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Pin description (continued) Pin No. Label External RMII0 interface (RMII_EN=1, P4EXT=1) 88, 87 RXD0_0, RXD0_1 84 RXDV0 80, 79 TXD0_0, TXD0_1 76 TXEN0 77 RMII0_CLK_OUT 89 RMII0_CLK_IN Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Type I RMII receive ...
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Pin description (continued) Pin No. Label External RMII1 interface (RMII_EN=1, MII1_DIS=0, MII1_PHY_MOD=1, P4EXT=1) 67, 66 RXD1_0, RXD1_1 63 RXDV1 61, 60 TXD1_0, TXD1_1 57 TXEN1 65 RMII1_PHY_CLK _OUT 59 RMII1_PHY_CLK _IN Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF ...
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Pin description (continued) Pin No. Label External RMII1 interface (RMII_EN=1, MII1_DIS=0, MII1_PHY_MOD=0, P4EXT=1) 67, 66 RXD1_0, RXD1_1 63 RXDV1 61, 60 TXD1_0, TXD1_1 57 TXEN1 58 RMII1_MAC_CLK _OUT 68 RMII1_MAC_CLK _IN Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF ...
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Pin description (continued) Pin No. Label External RMII2 interface (RMII_EN=1, MII2_EN=1, P4EXT=1) 108, 107 RXD2_0, RXD2_1 104 RXDV2 102,101 TXD2_0, TXD2_1 96 TXEN2 97 RMII2_CLK_OUT 109 RMII2_CLK_IN Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Type I RMII receive ...
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Pin description (continued) Pin No. Label Force mode (the setting is latched at the end of reset) 85, 76 P4_FORCE 86, 77 P3_FORCE 87, 78 P2_FORCE 88, 79 P1_FORCE 90, 80 P0_FORCE Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH ...
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Pin description (continued) Pin No. Label Force mode (the setting is latched at the end of reset) 103 P4_FORCE100 104 P3_FORCE100 105 P2_FORCE100 106 P1_FORCE100 107 P0_FORCE100 Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Type IPL1 Force port4 ...
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Pin description (continued) Pin No. Label Force mode (the setting is latched at the end of reset) 108 P4_FORCE_FULL IPL1 109 P3_FORCE_FULL IPL1 110 P2_FORCE_FULL IPL1 111 P1_FORCE_FULL IPL1 112 P0_FORCE_FULL IPL1 Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH ...
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Pin description (continued) Pin No. Label Transceiver 127, 128, RXIP0, RXIM0, 11, 12, RXIP1, RXIM1, 18, 19, RXIP2, RXIM2, 29, 30, RXIP3, RXIM3, 33, 34 RXIP4, RXIM4 3, 4, TXOP0, TXOM0 TXOP1, TXOM1, 21, 22, TXOP2, TXOM2, 26, ...
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Pin description (continued) Pin No. Label Misc. 123 X1 122 X2 93 RESETB 52 TEST2 EEPROM 53 SCL IPL/O After reset used as clock pin SCL of EEPROM. Its period is 54 SDA IPH/O After reset ...
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Pin description (continued) Pin No. Label LED 92, 91 LED_SEL[1:0] 110, 107, LED_LINK[4:0] 104, 101, 96 111, 108, LED_SPEED[4:0] 105, 102, 97 112, 109, LED_FULL[4:0] 106, 103, 100 Note: LED_SPEED[0] shows collision information for all ports. LED_SPEED[4:1] is undefined. Copyright ...
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Pin description (continued) Pin No. Label Dual color mode LED (It is active when LED_SEL[1:0] is {0,1}.) 110, 107, LED_LINK[4:0] 104, 101, 96 111, 108, LED_SPEED[4:0] 105, 102, 97 112, 109, LED_FULL[4:0] 106, 103, 100 Serial LED (MII2_EN=1) 112 SDATA ...
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Functional Description 2.1 Flow control IP175C/IP175CH supports the standard 802.3X flow control frames on both transmit and receive sides. On the receive side, if IP175C/IP175CH receives a pause control frame, the IP175C/IP175CH will defer transmitting next normal frame; on ...
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Tag VLAN / Tag and un-tag function 2.5.1 Tag and un-tag function IP175C/IP175CH inserts or removes a tag of a frame if tagging/ un-tagging function is enabled enabled by programming MII register 29.23. The operation is illustrated ...
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MII/RMII IP175C/IP175CH supports three MII/RMII ports. The block diagram and detail configuration are shown below noted that MII2 and MII1 MAC mode can’t be enabled at the same time. That is, user should not use MII2 if ...
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... To define the speed, duplex and pause of MII port The speed and duplex of MII port can be configured through pins or registers. IP175C/IP175CH’s MII register is not fully compatible to IP175A’s. User has to fill MII register 29.31 with 16’h175C before accessing MII registers. The details are shown in the following tables. ...
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MII1 PHY mode (interface to an external MAC, MII registers can be accessed via MDC0, MDIO0) The PHY address of MII1 PHY mode is 4. Pin MII1 speed/duplex/ -- pause MII1 MAC mode (interface to an external PHY), there are ...
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MII2 PHY mode (interface to an external MAC, MII registers can be accessed via MDC0, MDIO0) Pin MII2 speed P3_FORCE_100 MII2 duplex P3_FORCE_FULL P3_FORCE_FULL MII2 pause -- MII2 MAC mode (interface to an external PHY), there are two ways to ...
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The application circuit of RMII (P4EXT=1, P4MII_SNI=0, RMII_EN=1) When RMII mode is enabled, IP175C/IP175CH supports reference clock RMII_CLK_OUT for each RMII port. The clock is used by the external PHY (or MAC) and 175C itself. The following circuit diagram is ...
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The following circuit diagram is the RMII circuit of MII1 MAC mode. IP175C RMII_MAC_CLK_OUT The following circuit is the RMII circuit of MII1 PHY mode. IP175C RMII_PHY_CLK_OUT Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF TXD1_0 TXD0 TXD1_1 TXD1 ...
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SMART MAC IP175C/IP175CH supports SMART MAC function to solve locked Card’s ID issue. The SMART MAC function can be configured to 4LAN+1WAN, 3LAN+2WAN, 2LAN+3WAN or 1LAN+4WAN. The following example illustrates the behavior of IP175C/IP175CH SMART MAC function for 4LAN ...
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A programming example of SMART MAC example Register Content Tag/ un-tag function setup 29.23[0] 0 29.23[1] 1 29.23[10:6] 11111 29.23[15:11] 00000 PVID function setup 29.24~27 16’h0001 29.28 16’h0002 29.30 16’h0002 VLAN Mask function setup 30.1[13:8] 6’h2f 30.1[5:0] 6’h30 SMART MAC ...
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Packet from LAN to WAN 1. PC0 sends a packet to a LAN port with SA equal to PC0 without PVID or PVID equal IP175C/IP175CH forwards the packet to CPU (MII0) with PVID equal to 1. ...
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Built in regulator IP175C/IP175CH is built in one linear regulator. It use pin 120 REG_OUT to control an external transistor to generator a stable voltage source. IP175C/IP175CH generates a voltage source between 1.70v ~ 2.00v. Copyright © 2004, IC ...
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CoS IP175C/IP175CH supports two type of CoS. One is port base priority and the other is frame base priority. IP175C/IP175CH supports two levels of priority queues. 2.9.1 Port base priority The packets received from high priority port will be ...
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IPv4/IPv6 DiffServ IP175C/IP175CH checks the DiffServ field of a IPv4 frame or Traffic class field [7:2] (TC[7:2 IPv6 frame and uses them to decide the frame’s priority if MII register 30.27.0 DIFFSEV_EN is enabled. IP175C/IP175CH uses DiffServ ...
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Spanning tree IP175C/IP175CH supports spanning tree function with the following features: 1. Detect BPDU frames by examining multicast address (01-80-c2-00-00-00). 2. Forward BPDU packets to CPU through MII0 and add special tag for source port information. 3. Forward BPDU ...
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Special tag IP175C/IP175CH supports special tag function to exchange switching information with CPU without involving VLAN tag information. The special tag function is enabled by programming MII register 30.16.7 STAG_EN. 2.11.1 From CPU to switch When special tag function ...
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Static MAC address table IP175C/IP175CH supports a static MAC address table, which contains two MAC address. When IP175C/IP175CH receives a packet whose destination address matches the pre-defined MAC address in the table, it forwards the packets to a specfic ...
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Serial mode LED When MII/RMII2 is enabled, there are no enough pins for LED and IP175C/IP175CH sends out LED information through pin 111 SCLK and pin112 SDATA necessary to use TTL chip to decode and drive LED. ...
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IP175C/IP175CH supports link LED only.) SDATA A SCLK CLK 74HC164 VDD B CLR Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF VDD QA PORT 4 LINK/ACT LED QB PORT 3 LINK/ACT LED QC PORT 2 LINK/ACT LED ...
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LED Blink Timing LED mode Serial mode update period Active led blink Collision led blink Link quality fail blink Neon like LED(initial setup LED) On 286ms -> Off 2s -> On 286ms -> Off 2s … Copyright © 2004, ...
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Serial management interface 175C supports two serial management interfaces (SMI). User can access IP175C/IP175CH’s MII registers through MDC0 and MDIO0. Its format is shown in the following table. To access MII register in IP175C/IP175CH, MDC should be at least ...
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The application of SMI IP175C Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF MDC0 MDC MAC 1 MDIO0 MDIO MDC MAC 2 MDIO Only one MAC is allowed to access the MDC0,MDIO0. MDC1 MDC PHY1 MDIO1 MDIO MDC PHY2 ...
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Force mode of PHY Px_FORCE Px_FORCE_100 Px_FORCE_FULL IP175C/IP175CH’s capability IP175C/IP175CH’s link result Link partner’s (Nway enabled with all capability) link result Note: Px_FORCE, Px_FORCE_100,and Px_FORCE_full are force mode configuration pins port number from 0 to ...
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Setting from MDC/MDIO Duplex mode Full duplex PHY 4 MII register 0 bit 8 Half duplex PHY 4 MII register 0 bit 8 Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF MII register 57/111 Data Sheet Setting value ...
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MII registers of PHY Register 0 Control Register 1 Status Register 2 PHY Identifier 1 Register 3 PHY Identifier 2 Register 4 Auto-Negotiation Advertisement Register 5 Auto-Negotiation Link Partner Ability Register 6 Auto-Negotiation Expansion Registers X1: 5 ports share ...
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Register descriptions R/W = Read/Write Self-Clearing Read Only Latching Low Latching High MII register 0 of PHY0~4 (Each PHY has its own MII register 0 with different PHY address) PHY MII ROM ...
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MII register 1 of PHY0~4 (Each PHY has its own MII register 1 with different PHY address) PHY MII ROM R/W Status register 4~0 1. 100Base-T4 capable 4~0 1. 100Base-X full duplex Capable 4~0 1.13 -- ...
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MII register 1 of PHY0~4 (Each PHY has its own MII register 1 with different PHY address) PHY MII ROM R/W Status register 4~0 1 4~0 1.1 -- 4~0 1 Extended capability Copyright © 2004, ...
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MII register 2 of PHY0~4 (5 PHYs share the MII register) PHY MII ROM R/W PHY Identifier 1 register 4 IP175C/IP175CH OUI (Organizationally Unique Identifier) ID, MII register 3 of PHY0~4 (5 PHYs share the MII register) ...
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MII register 4 of PHY0~4 (Each PHY has its own MII register 4 with different PHY address) PHY MII ROM R/W Auto-Negotiation Advertisement register 4~0 4. Next Page 4~0 4. Reserved by IEEE, write as 0, ...
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MII register 5 of PHY0~4 (Each PHY has its own MII register 5 with different PHY address) PHY MII ROM R/W Auto-Negotiation Link Partner Ability register 4~0 5.15 RO Next Page 4~0 5.14 RO Acknowledge 4~0 5.13 RO Remote Fault ...
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MII register 6 of PHY0~4 (Each PHY has its own MII register 6 with different PHY address) PHY MII ROM R/W Auto-Negotiation Expansion register 4~0 6[15: Reserved 4~0 6 fault has been detected via ...
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MII registers of Switch controller PHY MII ROM R/W 29 18.15 2.1 R/W LED_SEL [1:0] 18.14 2.0 29 18.13 4.7 R/W 29 18.12 4.4 R/W 29 18.11 4.2 R/W 29 18.10 4.3 R/W Copyright © 2004, IC Plus Corp. ...
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PHY MII ROM R/W 29 18.5 6.7 R/W Reserved 29 18.4 6.5 R/W HASH_MODE 29 18.3 6.4 R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description The default value must be adopted for normal operation latched ...
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PHY MII ROM R/W 29 19.15 14.7 R/W 19.14 14.6 R/W 19.13 14.5 R/W Port0 high priority port enable 19[12.8] 14[4:0] R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description Port0 VLAN look up table Port5 and port0 ...
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PHY MII ROM R/W 29 19.7 15.7 R/W 19.6 15.6 R/W 19.5 15.5 R/W Port1 high priority port enable 19[4:0] 15[4:0] R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description Port1 VLAN look up table Port5 and port1 ...
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PHY MII ROM R/W 29 20.15 16.7 R/W 20.14 16.6 R/W 20.13 16.5 R/W Port2 high priority port enable 20[12:8] 16[4:0] R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description Port2 VLAN look up table Port5 and port2 ...
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PHY MII ROM R/W 29 20.7 17.7 R/W Port3 VLAN look up table 20.6 17.6 R/W 20.5 17.5 R/W Port3 high priority port enable 20[4:0] 17[4:0] R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description Port5 and port3 ...
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PHY MII ROM R/W 29 21.15 18.7 R/W Port4 VLAN look up table 21.14 18.6 R/W 21.13 18.5 R/W 21[12:8] 18[4:0] R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description Port5 and port4 are in the same VLAN ...
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PHY MII ROM R/W 29 22.15 19.4 R/W 29 22.14 19.3 R/W 29 22.13 19.2 R/W 29 22.12 19.1 R/W 29 22.11 19.0 R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description P4_FORCE Port4 force mode enable 1: ...
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PHY MII ROM R/W 29 22.10 20.4 R/W P4EXT=0 1: force port4 to be 100M 0: force port4 to be 10M 29 22.9 20.3 R/W P4EXT=0 1: force port3 to be 100M 0: force port3 to be 10M 29 22.8 ...
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PHY MII ROM R/W 29 22.5 21.4 R/W P4EXT=0 1: force port4 to be full duplex 0: force port4 to be half duplex 29 22.4 21.3 R/W P4EXT=0 1: force port3 to be full duplex 0: force port3 to be ...
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Tag register 10 PHY MII ROM R/W 29 23[15:11] 22[4:0] R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description ADD_TAG. Add VLAN tag Portx adds a VLAN tag defined in vlan_tag_x to each outgoing packet Bit 11 1: ...
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Tag register 11 PHY MII ROM R/W 29 23[10:6] 23[4:0] R/W 23.1 22.5 R/W 23.0 23.5 R/W REMOVE_TAG. Remove VLAN tag Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description REMOVE_TAG. Remove VLAN tag Bit 6 1: port0 removes ...
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Tag register 1~9 PHY MII ROM R 25[7:0] R/W VLAN_TAG_0. Port0 default VLAN tag value 24[7: 27[7:0] R/W VLAN_TAG_1. Port1 default VLAN tag value 26[7: 29[7:0] 28[7: 31[7:0] R/W VLAN_TAG_3. Port3 default ...
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... Description This register defines the VLAN tag of an un-tagged packet from port 5. Description IP175C/IP175CH MII register don’t support IP175A compatible mode. If the value of this register is 16’h175A, please fill this register with 16’h175C. Note1: The default value is 16’h175A if p4ext is 1, MII1_dis is, 0 and mii1_phy_mod is 1 ...
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PHY MII ROM R R/W Software reset register Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description IP175C/IP175CH is reset if uses write “175C”to this register self-cleared. The reset period is around 2ms. User ...
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Tag VLAN register 2 PHY MII ROM R/W 30 1[5:0] 39[5:0] R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description TAG_VLAN_MASK_0[5:0]. Tag VLAN 0 output port mask The mask is valid only if MII register 9.7 TAG_VLAN_EN is ...
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Tag VLAN register 3~17 PHY MII ROM R/W 30 1[13:8] 40[5:0] R/W TAG_VLAN_MASK_1[5:0]. Tag VLAN 1 output port mask 2[13:8] 42[5:0] R/W TAG_VLAN_MASK_3[5:0]. Tag VLAN 3 output port mask 2[5:0] 41[5:0] R/W TAG_VLAN_MASK_2[5:0]. Tag VLAN 2 output port mask 3[13:8] ...
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Router control register 1 PHY MII ROM R/W 30 9[12:8] 56[4:0] R/W 30 9.7 55.7 R/W 9[6:4] 55[6:4] R/W 30 9.3 55.3 R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description WAN_PORTS[4:0]. WAN ports for router application It ...
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PHY MII ROM R/W 30 9[2:0] 55[2:0] R/W LAN_GROUPS[2:0]. Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description Number of VLAN groups of LAN ports in a router application It defines the VLANs used by LAN ports. Each VLAN ...
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Router control register 2 PHY MII ROM R/W 30 10[5:0] 57[5:0] R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description PORT_LOCK_EN[5:0]. Lock port MAC address 1: enable 0: disable User has to reset IP175C/IP175CH by writing 16’h175C to ...
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Switch control register 3 PHY MII ROM R/W 30 11[15:14] 59[7:6] R/W BF_STM_THR_SEL[1:0]. 11[13:12] 59[5:4] R/W The default value should be adopted for normal operation. 11[11:10] 59[3:2] R/W The default value should be adopted for normal operation. 11[9:8] 59[1:0] R/W ...
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PHY MII ROM R/W 30 12.8 4.6 R/W BW_EN_QM 12.7 60.7 R/W 12.5 60.5 R/W 12.4 60.4 R/W PRIORITY_RATE 12.1 60.1 R/W Reserved (Must to be keep at 1’b1) 12.0 60.0 R/W HP_DIS_FLOW_EN Copyright © 2004, IC Plus Corp. IP175C/IP175C ...
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PHY MII ROM R/W 30 13[3:0] 96[3:0] R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description RESERVED_ADD_FORWARD[3:0] BIT3 Reserved MAC address (0180C2000010-0180C20000FF) 1: forward (default), 0: discard. BIT2 Reserved MAC address (0180C2000002- 0180C200000F) 1: forward (default), 0: discard. ...
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Spanning tree register PHY MII ROM R/W 30 16. 16.12 66.4 R/W Learning enable 16.11 66.3 R/W Learning enable 16.10 66.2 R/W Learning enable 16.9 66.1 R/W Learning enable 16.8 66.0 R/W Learning enable 16.7 65.7 R/W Stag_en ...
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PHY MII ROM R/W 30 17[14:13] 11[5:4] R/W Drive 17.12 17.11 10.5 R/W 17.10 10.4 R/W 17.9 10.1 R/W 17.8 11.3 R/W 17.7 11.2 R/W 17.6 11.1 R/W 17[5:0] 12[5:0] R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF ...
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PHY MII ROM R/W 30 18. mii1_full 18. mii1_speed10 18. mii0_full 18. mii0_speed10 18.11 12.6 R/W allpass 18.10 6.1 R/W modbck 18.9 6.2 R/W twopart 18.8 5.3 R/W bp_kind 18.7 13.7 R/W ...
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PHY MII ROM R R/W static_mac_0[15: R/W static_mac_0[31:16 R/W static_mac_0[47:32 R/W static_mac_1[15: R/W static_mac_1[31:16 R/W static_mac_1[47:32] 77 ...
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PHY MII ROM R/W 30 26.15 80.7 R/W static_overide_1 30 26.14 80.6 R/W static_valid_1 30 26[13:8] 80[5:0] R/W static_port_mask_1 30 26.7 79.7 R/W static_overide_0 30 26.6 79.6 R/W static_valid_0 30 26[5:0] 79[5:0] R/W static_port_mask_0 Copyright © 2004, IC Plus Corp. ...
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PHY MII ROM R/W 30 27.8 5.0 R/W MBSTM DISABLE 30 27.0 81.0 R/W DIFFSEV_EN 30 28 83, 82 R/W DSCP[15: 85, 84 R/W DSCP[31:16 87, 86 R/W DSCP[47:32 89, 88 R/W DSCP[63:48] Copyright ...
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PHY MII ROM R/W 31 2[14:12] 95[6:4] R/W 31 2[10:8] 95[2:0] R/W 31 2[6:4] 94[6:4] R/W BW_CONTROL_P4_TX[2:0] 31 2[2:0] 94[2:0] R/W BW_CONTROL_P4_RX[2:0] 31 1[14:12] 93[6:4] R/W BW_CONTROL_P3_TX[2:0] 31 1[10:8] 93[2:0] R/W BW_CONTROL_P3_RX[2:0] 31 1[6:4] 92[6:4] R/W BW_CONTROL_P2_TX[2:0] 31 1[2:0] 92[2:0] ...
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MII0 MAC mode register PHY MII ROM R Flow control capability of the link partner of external PHY on MII0 31 3. Mac_force[ MII0_link 31 3[12:8] 98[4:0] R/W Capability of ...
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MII1 MAC mode or MII2 MAC mode register (Only one is active at the same time.) PHY MII ROM R Flow control capability of the link partner of external PHY on MII1 31 4. ...
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MII1, MII1 and MII2 control register PHY MII ROM R/W 31 5.15 7.0 R/W P4EXT 5.12 7.4 R/W MII1_PHY_MOD 31 5.11 60.2 R/W 31 5.10 60.3 R/W 31 5.9 3.5 R/W ...
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PHY MII ROM R/W 31 5.5 3.1 R/W MII2_PHY_COL_DELAY 31 5.4 3.0 R/W MII0_PHY_COL_DELAY 31 5.2 2.4 R/W MII2_EN 31 5.1 2.3 R/W SERIAL_LED_MODE 31 5.0 2.2 R/W MII2_MAC_MOD Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description 0: ...
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PHY MII ROM R/W 31 6[15 MII1 flow control ability 31 6[14 MII0 flow control ability 31 6.1 9.1 R/W MDIX_FORCE 31 6.0 9.0 R/W Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Description 1: ...
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Electrical Characteristics 3.1 Absolute Maximum Rating Stresses exceed those values listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional performance and device reliability are not guaranteed under these conditions. All voltages are specified with respect ...
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AC Timing 3.3.1 Reset Timing Description X1 valid period before reset released Reset period MII clock comes out period after reset released Power on VCC OSCI (X1) X1 valid period before reset released resetb MII clock 3.3.2 PHY Mode ...
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Receive Timing Symbol T Receive clock period 100M MII RxClk T Receive clock period 10M MII RxClk T MII_RXCLK falling edge to RXDV, RXD dRxClk MII_RXCLK xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx RXDV, RXD[3:0] xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Copyright © 2004, ...
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MAC Mode MII Timing a. Receive Timing Requirements Symbol T Receive clock period 100M MII RxClk T Receive clock period 10M MII RxClk T RXDV, RXD to MII_RXCLK setup time sRxClk T RXDV, RXD to MII_RXCLK hold time hRxClk ...
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RMII Timing a. Receive Timing Requirements Symbol T Receive clock period RxClk T RXDV, RXD to MII_CLK_IN setup time sRxClk T RXDV, RXD to MII_CLK_IN hold time hRxClk M II_C LK _IN xxxxxxxxxxxxxxxxxx ...
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SNI Timing a. Transmit Timing Requirements Symbol T Transmit clock period TxClk T TXEN, TXD to MII_TXCLK setup time sTxClk T TXEN, TXD to MII_TXCLK hold time hTxClk M II_T xxxxxxxxxxxxxxxxx ...
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SMI Timing a. MDC0/MDIO0 Timing Symbol T MDC0 High Time ch T MDC0 Low Time cl T MDC0 period cm T MDIO0 output delay md T MDIO0 setup time mh T MDIO0 hold time ...
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MDC1/ MDIO1 Timing Symbol T MDC1 High Time ch T MDC1 Low Time cl T MDC1 period cm T MDIO1 output delay md T MDIO1 setup time ms T MDIO1 hold time ...
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EEPROM Timing a. Symbol T Receive clock period SCL T SDA to SCL setup time sSCL T SDA to SCL hold time hSCL xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx b. Symbol T ...
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Order Information Part No. IP175C 128-PIN PQFP IP175C LF 128-PIN PQFP IP175CH 128-PIN PQFP IP175CH LF 128-PIN PQFP Copyright © 2004, IC Plus Corp. IP175C/IP175C LF/IP175CH/IP175CH LF Package Notice - Lead free For fiber application For fiber application Lead ...
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Package Detail 128 PQFP Outline Dimensions 128 Dimensions In Inches Symbol Min. Nom. Max. A1 0.010 0.014 0.018 A2 0.107 0.112 0.117 b 0.007 0.009 0.011 c 0.004 0.006 ...