PEEL18CV8 ETC-unknow, PEEL18CV8 Datasheet
PEEL18CV8
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PEEL18CV8 Summary of contents
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... Super sets PLDs (PAL, GAL, EPLD) - Enhanced Architecture fits more logic than ordinary PLDs The PEEL18CV8 architecture allows it to replace over 20 standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also pro- vides additional architecture features so more logic can be put into every design. ICT’s JEDEC file translator instantly converts to the PEEL18CV8 existing 20-pin PLDs without the need to rework the existing design ...
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... International CMOS Technology Figure 3 PEEL18CV8 Logic Array Diagram 2 PEEL TM 18CV8 04-02-004H ...
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... Programmable I/O Macrocell The unique twelve-configuration output macrocell provides complete control over the architecture of each output. The ability to configure each output independently permits users to tailor the configuration of the PEEL18CV8 to the precise requirements of their designs. Macrocell Architecture Each I/O macrocell, as shown in Figure 4, consists type flip-flop and two signal-select multiplexers ...
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... Programming Support ICT’s JEDEC file translator allows easy conversion of exist- ing 20 pin PLD designs to the PEEL18CV8, without the need for redesign. ICT supports a broad range of popular third party design entry systems, including Data I/O Synario and Abel, Logical Devices CUPL and others ...
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... International CMOS Technology Figure 5 Equivalent Circuits for the Twelve Configurations of the PEEL18CV8 I/O Macrocell Configuration Input/Feedback Select # Bi-directional I Bi-directional I Bi-directional I Bi-directional I Combinatorial Feedback Combinatorial Feedback ...
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International CMOS Technology Absolute Maximum Ratings Symbol Parameter V Supply Voltage Voltage Applied to Any Pin I Output Current O T Storage Temperature ST T Lead Temperature LT Operating Range Symbol Parameter Vcc ...
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International CMOS Technology A.C. Electrical Characteristics 8 Over the operating range Symbol Parameter Input to non-registered output Input to output enable Input to output disable t Clock to ...
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... TTL -5/-7 Ordering Information Part Number PEEL18CV8J-5 PEEL18CV8P-7 PEEL18CV8J-7 PEEL18CV8S-7 PEEL18CV8P-10 PEEL18CV8PI-10 PEEL18CV8J-10 PEEL18CV8JI-10 PEEL18CV8S-10 PEEL18CV8SI-10 PEEL18CV8T-10 PEEL18CV8TI-10 PEEL18CV8P-15 PEEL18CV8PI-15 PEEL18CV8J-15 PEEL18CV8JI-15 PEEL18CV8S-15 PEEL18CV8SI-15 PEEL18CV8T-15 PEEL18CV8TI-15 PEEL18CV8P-25 PEEL18CV8PI-25 PEEL18CV8J-25 PEEL18CV8JI-25 PEEL18CV8S-25 PEEL18CV8SI-25 PEEL18CV8T-25 PEEL18CV8TI-25 Thevenin V L Equivalent R L Output 480k ...
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... Technology Part Number Package P = 20-pin Plastic 300mil DIP J = 20-pin Plastic (J) Leaded Chip Carrier (PLCC 20-pin SOIC 300 mil Gullwing T = 20-pin TSSOP 170 mil Device Suffix PEEL18CV8 PI-25 Speed –5 = 5ns t –7 = 7.5ns t –10 = 10ns t –15 = 15ns t –25 = 25ns t Temperature Range (Blank) = Commercial 0 to +70°C ...
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International CMOS Technology 10 PEEL TM 18CV8 04-02-004H ...