MTD502EF MYSON, MTD502EF Datasheet

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MTD502EF

Manufacturer Part Number
MTD502EF
Description
2 port 10M/100M switch with build_in memory
Manufacturer
MYSON
Datasheet
FEATURES
• IEEE802.3 and IEEE802.3u compliant.
• Single chip, low cost, two port switch controller.
• Build_in embedded memory on chip for packet
• Provide 2 MII/RMII (Reduced Media Indepen-
• A flexible MII interface design can directly con-
• Support half/full duplex operation per port.
• Optional back_pressure control for half_duplex
• Provide “store and forward” switching, and for-
• Support up to 2048 MAC addresses filtering
• Low power CMOS design, with single 3.3V
• Provide 128 pin PQFP package (MTD502EF),
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of
the product.
BLOCK DIAGRAM
buffering.
dent Interface) ports.
nect with standard MII or pseudo MII.
mode.
warding rate at full_wire speed.
database, and automatical address aging_out
function (300 secs).
supply voltage, 50 MHZ operation.
and 80 pin LQFP package (MTD502EG).
2 Port 10M/100M Switch With Build_in Memory
MYSON
TECHNOLOGY
Two
Port
Switch
Engine
Embedded Memory
Port0 DMA
Port1 DMA
1/20
100M two port switch controller with build_in
embedded memory. It supports 2 MII/RMII ports
for 10M/100M operation, and both can operate
under half or full duplex mode.
port bridge or dual speed hub application, and no
need any external memory buffers in application
design. The flexible MII interface design can
directly connect with pseudo MII interface
(Am79c901, HomePNA PHY).
ing, address filtering, learning, and aging func-
tion, and have an optional back_presure control
implemented in half duplex mode.
address filtering database, which can recognize
up to 2048 MAC addresses. It also support an
automatical aging function for address table
updating (aging time is 300 secs default).
GENERAL DESCRIPTION
The MTD502E is a highly integrated, 10M/
The MTD502E is an ideal solution for two
The MTD502E provides packet forward-
The MTD502E supports an effective
MAC0
MAC1
MTD502E Revision 1.3 12/07/2000
MII0
MII1
MTD502E

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MTD502EF Summary of contents

Page 1

... Support up to 2048 MAC addresses filtering database, and automatical address aging_out function (300 secs). • Low power CMOS design, with single 3.3V supply voltage, 50 MHZ operation. • Provide 128 pin PQFP package (MTD502EF), and 80 pin LQFP package (MTD502EG). BLOCK DIAGRAM Two Port ...

Page 2

... MTD502E 10M/100M Repeater (Without 2P_sw) This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product.E MTD502E HomePNA ...

Page 3

... MYSON TECHNOLOGY 1.0 PIN CONNECTION (under MII mode) 1) 128 Pin PQFP (MTD502EF) VCC 103 NC 104 GND 105 NC 106 NC 107 NC 108 NC 109 NC 110 NC 111 NC 112 NC 113 CLK25OUT 114 NC 115 NC 116 GND 117 NC 118 NC 119 NC 120 VCC 121 SYSCLK 122 GND 123 NC 124 NC 125 ...

Page 4

... MYSON TECHNOLOGY 2) 80 Pin LQFP (MTD502EG) NC VCC NC GND CLK25OUT VCC SYSCLK NC RSTB LINK0 TXD0_3 VCC TXD0_2 MTD502EG 4/20 MTD502E ...

Page 5

... MYSON TECHNOLOGY 2.0 PIN DESCRIPTIONS MTD502EF (128PQFP) Pin Definition Mapping Under Different Configurations MII Phy_MII Pin No. I/O mode mode 1 I LINK0 (NC TXD0_3 RXD0_3 3 VCC 4 O TXD0_2 RXD0_2 5 O (NC) CRS0 6~8 I (NC) (NC TXD0_1 RXD0_1 10 O TXD0_0 RXD0_0 11 O TXEN0 RXDV0 12 I TXC0 (NC) ...

Page 6

... MYSON TECHNOLOGY MTD502EF (128PQFP) Pin Definition Mapping Under Different Configurations MII Phy_MII Pin No. I/O mode mode 46 GND 47 I RXC1 (NC) 48~50 O (NC) (NC RXD1_0 (NC RXD1_1 (NC FULL1 (NC) 54~56 O (NC) (NC RXD1_2 (NC RXD1_3 (NC) 59 VCC 60 GND 61 I RXDV1 (NC CRS1 (NC COL1 ...

Page 7

... MYSON TECHNOLOGY MTD502EF (128PQFP) Pin Definition Mapping Under Different Configurations MII Phy_MII Pin No. I/O mode mode 94 IO FdCo0_D FdCo0_D FdCo0_D FdCo0_D Port0: FULL/COL LED display, low_active LnAc1_D LnAc1_D LnAc1_D LnAc1_D Port1: Link_Activity LED display, low_active LnAc0_D LnAc0_D LnAc0_D LnAc0_D Port0: Link_Activity LED display, low_active. * ...

Page 8

... IO (NC) (NC) 128 I RSTB RSTB note: input signal LINK,SPEED,FULL from PHY device are low_active definnition. MTD502EF(128PQFP) Jumper Setting Table After Power On Reset Pin No. IO Setting Function 5 IO 2P_Sw Enable 18 IO Back Pressure Disable Jumper setting function after power on reset. 95 ...

Page 9

... MYSON TECHNOLOGY MTD502EF(128PQFP) Jumper Setting Table After Power On Reset Pin No. IO Setting Function 101 IO P0_Bkoff_4 Enable 102 IO DeviceID[4] 104 IO DeviceID[3] 106 IO DeviceID[2] 107 IO DeviceID[1] 108 IO DeviceID[0] 109 IO P1_CRCchk Disable Descriptions Jumper setting function after power on reset. -external pull_high = 1, means Port 0 MAC backoff engine is using limit_4 modified method ...

Page 10

... MYSON TECHNOLOGY MTD502EF(128PQFP) Jumper Setting Table After Power On Reset Pin No. IO Setting Function 110 IO P0_CRCchk Disable 126 IO VLAN tag Enable Descriptions Jumper setting function after power on reset. -external pull_high = 1, means Port0 CRC check and drop function is disabled. -external pull_low = 0, means Port0 CRC check and drop function is enabled ...

Page 11

... MYSON TECHNOLOGY 3.0 MTD502EG (80LQFP) PIN DESCRIPTIONS MTD502EG(80LQFP) Pin Definition Mapping Under Different Configurations MII Phy_MII Pin No. I/O mode 1 O (NC TXD0_1 RXD0_1 3 O TXD0_0 RXD0_0 4 O TXEN0 5 I TXC0 6 GND 7 I RXC0 8 O (NC (NC (NC RXD0_0 TXD0_0 RXD0_0 TXD0_0 12 I RXD0_1 TXD0_1 RXD0_1 TXD0_1 ...

Page 12

... MYSON TECHNOLOGY MTD502EG(80LQFP) Pin Definition Mapping Under Different Configurations MII Phy_MII Pin No. I/O mode mode 40 I COL1 (NC) 41 VCC 42 I SPEED1 (NC) 43 VCC 44 VCC 45 GND 46 GND 47 GND 48 GND 49 IO Co1_D Co1_D 50 IO Co0_D Co0_D 51 GND 52 GND 53 IO FdCo1_D FdCo1_D FdCo1_D FdCo1_D Port1: FULL/COL LED display, ...

Page 13

... MYSON TECHNOLOGY MTD502EG(80LQFP) Pin Definition Mapping Under Different Configurations MII Phy_MII Pin No. I/O mode 56 IO LnAc0_D LnAc0_D LnAc0_D LnAc0_D Port0: Link_Activity LED display LnRx1_D LnRx1_D LnRx1_D LnRx1_D Port1: Link_Rx LED display LnRx0_D LnRx0_D LnRx0_D LnRx0_D Port0: Link_Rx LED display, 59-61 IO (NC) ...

Page 14

... MYSON TECHNOLOGY MTD502EG(80LQFP) Jumper Setting Table After Power On Reset Pin No. IO Setting Function 1 IO 2P_Sw Enable 10 IO Back Pressure Disable Jumper setting function after power on reset P0_Rmii Enable 58 IO P0_Phy_Mode Enable Jumper setting function after power on reset P1_Bkoff_4 Enable ...

Page 15

... MYSON TECHNOLOGY MTD502EG(80LQFP) Jumper Setting Table After Power On Reset Pin No. IO Setting Function 63 IO DeviceID[ DeviceID[ DeviceID[ DeviceID[ P1_CRCchk Disable 69 IO P0_CRCchk Disable 71 IO VLAN tag Enable Descriptions Jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. ...

Page 16

... MYSON TECHNOLOGY 4.0 FUNCTIONAL DESCRIPTIONS The MTD502E implements a 10/100M two port switch for 10M/100M packet switching. Total 2K address entrys are provided for packets’ SA learning and DA routing; and also provide automatic aging function ( aging time = 300secs). When using in two port bridge application, the input packets from port0 will be stored in an embedded memory buffers of MTD502E first, while packets is good for for- warding ( CRC chech ok, 64Bytes < ...

Page 17

... MYSON TECHNOLOGY 5.0 Electrical Characteristics 5.1 Absolute Maximum Ratings Symbol Parameter V Power Supply Voltage CC V Input Voltage IN V Output Voltage OUT T Storage Temperature STG 5.2 Recommended Operating Conditions Symbol Parameter V Power Supply CC V Input Voltage IN Commercial Junction Operating Temperature T j Industrial Junction Operating Temperature 5 ...

Page 18

... MYSON TECHNOLOGY 5.4 Electrical Characteristics FIGURE 1. MII timing RXCLK0 CRS0/RXDV0 RXD0[3:0] TXCLK0 TXEN0 TXD0[3:0] Symbol Parameter T5 MII input setup time T6 MII input hold time T7 MII output setup time T8 MII output hold time FIGURE 2. RMII timing REFCLK CRSDV RXD[1:0] TXEN TXD[1:0] Symbol Parameter ...

Page 19

... MYSON TECHNOLOGY 6.0 128 pin PQFP Package Data 102 103 128 See Detail B See Detail A Seating Plane Gage Plane Detail A Symbol Note: 1.Dimension D1 & not include mold protrusion. But mold mismatch is included. Allowable protrusion is .25mm/.010” per side. ...

Page 20

... MYSON TECHNOLOGY 7.0 80 pin LQFP Package Data See Detail A Seating Plane Gage Plane L L1 Detail See Detail With Plating Base Metal Detail B 20/20 MTD502E Dimension in inch Dimension in mm Symbol Min Norm Max ...

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