JS28F256P30B95 NUMONYX Numonyx B.V, JS28F256P30B95 Datasheet
JS28F256P30B95
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JS28F256P30B95 Summary of contents
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Numonyx™ StrataFlash (P30) Product Features High performance — initial access — 52 MHz with zero wait states, 17ns clock-to-data output synchronous-burst read mode — asynchronous-page read mode — 4-, 8-, 16-, and continuous-word burst mode — ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR Legal L ines and D isc laim er s OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT ...
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P30 Contents 1.0 Introduction .............................................................................................................. 6 1.1 Nomenclature ..................................................................................................... 6 1.2 Acronyms........................................................................................................... 6 1.3 Conventions ....................................................................................................... 7 2.0 Functional Overview .................................................................................................. 8 2.1 Virtual Chip Enable Description.............................................................................. 8 3.0 Package Information ............................................................................................... 10 3.1 56-Lead TSOP................................................................................................... 10 3.2 64-Ball Easy ...
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WAIT Polarity .........................................................................................52 10.3.4 Data Hold ..............................................................................................53 10.3.5 WAIT Delay............................................................................................53 10.3.6 Burst Sequence ......................................................................................54 10.3.7 Clock Edge.............................................................................................54 10.3.8 Burst Wrap ............................................................................................55 10.3.9 Burst Length ..........................................................................................55 10.3.10 End of Word Line (EOWL) Considerations ...................................................55 11.0 Programming Operations .........................................................................................56 11.1 Word ...
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P30 Revision History Revision Date Revision April 2005 -001 August 2005 -002 September 2005 -003 November 2005 -004 February 2006 -005 April 2006 -006 May 2006 -007 May-2006 -008 June - 2007 -009 November 2007 -010 November 2007 11 November ...
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Introduction This document provides information about the Numonyx™ StrataFlash Memory (P30) product and describes its features, operation, and specifications. The Numonyx™ StrataFlash of Numonyx™ StrataFlash densities, the P30 device brings reliable, two-bit-per-cell storage technology to the embedded flash market ...
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P30 RFU: Reserved for Future Use SR: Status Register WSM: Write State Machine 1.3 Conventions VCC: Signal or voltage connection V : Signal or voltage level CC 0x: Hexadecimal number prefix 0b: Binary number prefix SR[4]: Denotes an individual register ...
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Functional Overview This section provides an overview of the features and capabilities of the P30. The P30 family provides density upgrades from 64-Mbit through 512-Mbit. This family of devices provides high performance at low voltage on a 16-bit data ...
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P30 Table 2: Virtual Chip Enable Truth Table for 512 Mb (Easy BGA & TSOP Packages) Die Selected Lower Param Die Upper Param Die November 2007 Order Number: 306666-11 CE# A25 Datasheet 9 ...
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Package Information 3.1 56-Lead TSOP Figure 1: TSOP Mechanical Specifications Z See Notes 1 and 3 Pin 1 See Detail A Detail A Table 3: TSOP Package Dimensions (Sheet Product Information Symbol Package Height A Standoff ...
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P30 Table 3: TSOP Package Dimensions (Sheet Product Information Symbol Lead Tip Length L Lead Count N Lead Tip Angle ý Seating Plane Coplanarity Y Lead to Package Offset Z Notes: 1. One dimple on package denotes ...
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Table 4: Easy BGA Package Dimensions Product Information Package Height (64/128/256-Mbit) Package Height (512-Mbit) Ball Height Package Body Thickness (64/128/256- Mbit) Package Body Thickness (512-Mbit) Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane ...
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P30 3.3 QUAD+ SCSP Packages Figure 3: 64/128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm) A1 Index Mark Top View - Ball Down ...
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Figure 4: 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm Index Mark Top View - Ball Down A2 Note: Dimensions A1, A2, ...
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P30 Figure 5: 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm Index Mark Top View - Ball Down A2 Dimensions Package ...
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Ballout and Signal Descriptions 4.1 Signal Ballout Figure 6: 56-Lead TSOP Pinout (64/128/256/512- Mbit) 1 A16 A15 2 3 A14 4 A13 5 A12 6 A11 7 A10 A23 10 A22 11 A21 12 VSS 13 ...
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P30 Figure 7: 64-Ball Easy BGA Ballout (64/128/256/512-Mbit VPP B A2 VSS A9 CE A10 A12 A11 RST# E DQ8 DQ1 DQ9 DQ3 F RFU DQ0 ...
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Figure 8: 88-Ball (80-Active Ball) QUAD+ SCSP Ballout Pin A18 C A5 RFU D A3 A17 DQ8 H RFU DQ0 J RFU F1-OE# K ...
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P30 4.2 Signal Descriptions This section has signal descriptions for the various P30 packages. Table 5: TSOP and Easy BGA Signal Descriptions (Sheet Symbol Type ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit: A[MAX:1] Input ...
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Table 5: TSOP and Easy BGA Signal Descriptions (Sheet Symbol Type Reserved for Future Use: Reserved by Numonyx for future device functionality and enhancement. RFU — These should be treated in the same way ...
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P30 Table 6: QUAD+ SCSP Signal Descriptions (Sheet Symbol Type Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited VCC Power when V CC VCCQ Power Output Power Supply: Output-driver source ...
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Memory Maps Table 7 through multiple 8-Mbit Programming Regions (see page 56). Table 7: Discrete Top Parameter Memory Maps (all packages) Size Blk (KB 3FC000 - 3FFFFF 32 63 3F0000 - 3F3FFF 128 62 3E0000 - 3EFFFF ...
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P30 Table 8: Discrete Bottom Parameter Memory Maps (all packages) Size Blk (KB) 128 10 070000 - 07FFFF 128 4 010000 - 01FFFF 32 3 00C000 - 00FFFF 32 0 000000 - 003FFF Size Blk (KB) 128 258 FF0000 - ...
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Table 9: 512-Mbit Top and Bottom Parameter Memory Map (Easy BGA and QUAD+ SCSP) (Sheet Die Stack Config 256-Mbit Bottom Parameter Die Note: Refer to the appropriate 256-Mbit Memory Map ( is referenced in K-Bytes where a ...
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P30 5.0 Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Table 10: Parameter Temperature under bias Storage temperature Voltage on any ...
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Electrical Specifications 6.1 DC Current Characteristics Table 12: DC Current Characteristics (Sheet Sym Parameter I Input Load Current LI Output I Leakage DQ[15:0], LO WAIT Current 64-Mbit 128-Mbit Standby, CCS CC I Power ...
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P30 Table 12: DC Current Characteristics (Sheet Sym Parameter I V Erase Current PPE PP Notes: 1. All currents are RMS unless noted. Typical values at typical the average current measured over any ...
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AC Characteristics 7.1 AC Test Conditions Figure 11: AC Input/Output Reference Waveform V CCQ Input V /2 CCQ 0V Note: AC test inputs are driven at V CCQ and fall times (10% to 90%) < 5 ns. Worst case ...
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P30 7.2 Capacitance Table 15: Capacitance Parameter Signals Address, Data, CE#, WE#, OE#, Input Capacitance RST#, CLK, ADV#, WP# Output Capacitance Data, WAIT Notes: 1. Capacitance values are for a single die; for 2-die and 4-die stacks, multiply the capacitance ...
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Table 16: AC Read Specifications for 64/128- Mbit Densities (Sheet Num Symbol R108 t Page address access APA R111 t RST# high to ADV# high phvh Clock Specifications R200 f CLK frequency CLK R201 t CLK period ...
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P30 Table 17: AC Read Specifications for 256/512-Mbit Densities (Sheet Num Symbol R3 t CE# low to output valid ELQV R4 t OE# low to output valid GLQV R5 t RST# high to output valid PHQV R6 ...
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Table 17: AC Read Specifications for 256/512-Mbit Densities (Sheet Num Symbol R301 t Address setup to CLK AVCH/L R302 t ADV# low setup to CLK VLCH/L R303 t CE# low setup to CLK ELCH/L R304 t CLK ...
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P30 Figure 14: Asynchronous Single-Word Read (ADV# Low) Address [A] ADV# CE# [E} OE# [G] R15 WAIT [ Data [D/Q] RST# [P] Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Figure 15: Asynchronous Single-Word ...
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Figure 16: Asynchronous Page-Mode Read Timing R2 A[Max:2] [A] A[1:0] R101 R105 R105 ADV# R3 CE# [E] R4 OE# [G] R15 WAIT [T] R7 DATA [D/Q] Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Figure 17: ...
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P30 Figure 18: Continuous Burst Read, Showing An Output Delay Timing R301 R302 R306 CLK [C] R2 R101 Address [A] R106 R105 R105 ADV# [V] R303 R102 R3 CE# [E] OE# [G] R15 WAIT [T] R7 Data [D/Q] Notes: 1. ...
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AC Write Specifications Table 19: AC Write Specifications Num Symbol W1 t RST# high recovery to WE# low PHWL W2 t CE# setup to WE# low ELWL W3 t WE# write pulse width low WLWH W4 t Data setup ...
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P30 Figure 20: Write-to-Write Timing W5 Address [A] W2 CE# [E} WE# [W] OE# [G] Data [D/Q] W1 RST# [P] Figure 21: Asynchronous Read-to-Write Timing R2 Address [A] R3 CE# [E} OE# [G] WE# [W] WAIT [ Data ...
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Figure 22: Write-to-Asynchronous Read Timing W5 Address [A] ADV# [V] W2 CE# [E} WE# [W] OE# [G] WAIT [T] Data [D/Q] W1 RST# [P] Figure 23: Synchronous Read-to-Write Timing R301 R302 R306 CLK [C] R2 R101 Address [ A] R105 ...
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P30 Figure 24: Write-to-Synchronous Read Timing CLK W5 Address [A] ADV# W2 CE# [ WE# [W] OE# [G] WAIT [T] W4 Data [D/Q] W1 RST# [P] Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation ...
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Table 20: Num Symbol Parameter W500 t 32-KByte Parameter ERS/PB Erase Time W501 t 128-KByte Main ERS/MB W600 t Program suspend SUSP/P Suspend W601 t Erase suspend SUSP/E Latency W602 t Erase to Suspend ERS/SUSP Notes: 1. Typical values measured ...
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P30 8.0 Power and Reset Specifications 8.1 Power-Up and Power-Down Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise V and V should attain their minimum operating voltage before applying V CC CCQ Power ...
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Figure 25: Reset Operation Waveforms (A) Reset during read mode (B) Reset during program or block erase P1 ≤ P2 (C) Reset during program or block erase P1 ≥ P2 (D) VCC Power-up to RST# high 8.3 Power Supply Decoupling ...
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P30 9.0 Device Operations This section provides an overview of device operations. The system CPU provides control of all in-system read, write, and erase operations of the device via the system bus. The on-chip Write State Machine (WSM) manages all ...
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Writes To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted. During a write operation, address and data are latched on the rising edge of WE# or CE#, whichever occurs first. shows ...
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P30 9.2 Device Commands Device operations are initiated by writing specific device commands to the Command User Interface (CUI). See commands are used to modify array data including Word Program and Block Erase commands. Writing either command to the CUI ...
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Command Definitions Valid device command codes and descriptions are shown in Table 24: Command Codes and Definitions (Sheet Mode Code Device Mode 0xFF Read Array Read Status 0x70 Register Read Device ID Read 0x90 or Configuration ...
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P30 Table 24: Command Codes and Definitions (Sheet Mode Code Device Mode 0x60 Lock Block Setup 0x01 Lock Block Block Locking/ Unlocking 0xD0 Unlock Block 0x2F Lock-Down Block Program Protection Protection 0xC0 Register Setup Read Configuration 0x60 ...
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Read Operations The device supports two read modes: asynchronous page mode and synchronous burst mode. Asynchronous page mode is the default read mode after device power- reset. The Read Configuration Register must be configured to enable synchronous ...
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P30 10.3 Read Configuration Register The Read Configuration Register (RCR) is used to select the read mode (synchronous or asynchronous), and it defines the synchronous burst characteristics of the device. To modify RCR settings, use the Configure Read Configuration Register ...
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Read Mode The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation for the device. When the RM bit is set, asynchronous page mode is selected (default). When RM is cleared, synchronous burst mode is selected. 10.3.2 ...
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P30 Figure 26: First-Access Latency Count CLK [C] Valid Address [A] Address ADV# [V] Code 0 (Reserved) Valid DQ [D/Q] Output 15-0 Code 1 (Reserved DQ [D/Q] 15-0 Code 2 DQ [D/Q] 15-0 Code 3 DQ [D/Q] 15-0 Code 4 ...
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Figure 27: Example Latency Count Setting using Code 3 CLK CE# ADV# A[MAX:0] D[15:0] 10.3.3 WAIT Polarity The WAIT Polarity bit (WP), RCR[10] determines the asserted level (V WAIT. When WP is set, WAIT is asserted high (default). When WP ...
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P30 Table 27: WAIT Functionality Table (Sheet Condition All Asynchronous Reads All Writes Notes: 1. Active: WAIT is asserted until data becomes valid, then deasserts 2. When OE during writes, WAIT = High-Z IH 10.3.4 ...
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Burst Sequence The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is supported. lengths, as well as the effect of the Burst Wrap (BW) setting. Table 28: Burst Sequence Word Ordering Start Burst Addr. Wrap 4-Word ...
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P30 10.3.8 Burst Wrap The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross word-length boundaries. When BW is set, burst wrapping does not occur (default). When BW ...
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Programming Operations The device supports three programming methods: Word Programming (40h/10h), Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h, D0h). See Section 9.0, “Device Operations” on page 43 commands issued to the device. The following sections describe ...
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P30 Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow, when word programming has completed. 11.1.1 Factory Word Programming Factory word programming is ...
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If an attempt is made to program past an erase-block boundary using the Buffered Program command, the device aborts the operation. This generates a command sequence error, and Status Register bits SR[5,4] are set. If Buffered programming is attempted while ...
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P30 Table 30: BEFP Considerations Parameter/Issue Cycling For optimum performance, cycling must be limited below 100 erase cycles per block. Programming blocks BEFP programs one block at a time; all buffer data must fall within a single block Suspend BEFP ...
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BEFP exit. After the buffer fill cycle, no write cycles should be issued to the device until SR[ and the device is ready for the next buffer fill. Note: Any spurious ...
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P30 11.6 Program Protection When absolute hardware write protection is provided for all device blocks below V PP level error. Block lock registers are not affected by the voltage ...
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Erase Operations Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits ...
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P30 during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend. During an erase suspend, deasserting CE# places the device in standby, reducing active current. V while ...
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Security Modes The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail. 13.1 Block Locking Individual instant block locking is used to protect user ...
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P30 13.1.4 Block Lock Status The Read Device Identifier command is used to determine a block’s lock status (see Section 14.2, “Read Device Identifier” on page addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 is ...
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If a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. However, the erase operation completes when it is resumed. Block lock operations cannot occur during a program suspend. See ...
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P30 The user-programmable Protection Registers contain one-time programmable (OTP) bits; when programmed, register bits cannot be erased. Each Protection Register can be accessed multiple times to program individual bits, as long as the register remains unlocked. Each Protection Register has ...
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Programming the Protection Registers To program any of the Protection Registers, first issue the Program Protection Register command at the parameter’s base address plus the offset to the desired Protection Register (see Section 9.2, “Device Commands” on page Protection ...
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P30 14.0 Special Read States The following sections describe non-array read states. Non-array reads can be performed in asynchronous read or synchronous burst mode. A non-array read operation occurs as asynchronous single-word mode. When non-array reads are performed in asynchronous ...
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Table 32: Status Register Description (Sheet Status Register (SR Status (VPPS Program Suspend Status (PSS) 1 Block-Locked Status (BLS) 0 BEFP Status (BWS) Note: Always clear the Status Register prior to resuming erase ...
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P30 Table 33: Device Identifier Information (Sheet Item Lock Register 1 128-bit User-Programmable Protection Registers Notes: 1. BBA = Block Base Address. Table 34: Device ID codes ID Code Type Device Code Note: The 512-Mbit devices do ...
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Appendix A Write State Machine Figure 32 through based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read Array, Read Device ID, CFI Query or ...
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P30 Figure 33: Write State Machine—Next State Table (Sheet Read Word Current Chip (2) (3,4) Array Program (7) State (FFH) (10H/40H) Setup Word Program Busy in Erase Suspend Busy Word Program in Erase Suspend Word Program Suspend ...
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Figure 34: Write State Machine—Next State Table (Sheet OTP Current Chip Setup (7) State (C0H) OTP Ready Setup Ready Lock/CR Setup (Lock Error) Setup OTP Busy Setup Busy Word Program Suspend Setup BP Load 1 BP Confirm ...
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P30 Figure 35: Write State Machine—Next State Table (Sheet OTP Current Chip Setup (7) State (C0H) Setup Busy Word Program in Erase Suspend Suspend Setup BP Load 1 BP Confirm if Data load into Program Buffer is ...
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Figure 36: Write State Machine—Next State Table (Sheet Output Next State Table Word Read Program (2) Array Current chip state Setup (3,4) (FFH) (10H/40H) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, ...
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P30 Figure 37: Write State Machine—Next State Table (Sheet Output Next State Table Command Input to Chip and resulting Output Mux Next State OTP (4) Setup Current chip state (C0H) BEFP Setup, BEFP Pgm & Verify Busy, ...
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The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next state of ...
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P30 Appendix B Flowcharts Figure 38: Word Program Flowchart WORD PROGRAM PROCEDURE Start Write 0x40, (Setup) Word Address Write Data, (Confirm) Word Address Read Status Register No Yes 0 SR[7] = Suspend? 1 Full Status Check (if desired) Program Complete ...
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Figure 39: Program Suspend/Resume Flowchart PROGRAM SUSPEND / RESUME PROCEDURE Start Read Status Write 70 h Program Suspend Write B0h Any Address Read Status Register 0 SR Program 0 SR.2 = Completed 1 Read Array Write FFh Read ...
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P30 Figure 40: Buffer Program Flowchart Start Device Use Single Word Supports Buffer No Programming Writes? Yes Set Timeout or Loop Counter Get Next Target Address Issue Write to Buffer Command E8h and Block Address Read Status Register (at Block ...
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Figure 41: BEFP Flowchart BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) PROCEDURE Setup Phase Start V applied PP Block Unlocked W rite 80h @ st 1 Word Address W rite D0h @ st 1 Word Address BEFP Setup delay Read Status Reg. ...
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P30 Figure 42: Block Erase Flowchart BLOCK ERASE PROCEDURE Start Write 0x20, (Block Erase) Block Address Write 0xD0, (Erase Confirm) Block Address Read Status Register No Suspend 0 Yes SR[7] = Erase 1 Full Erase Status Check (if desired) Block ...
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Figure 43: Erase Suspend/Resume Flowchart ERASE SUSPEND / RESUME PROCEDURE Start Read Status Write 70h Any Address Erase Suspend Write B0h Any Address Read Status Register 0 SR Erase 0 SR.6 = Completed 1 Read Read or Program ...
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P30 Figure 44: Block Lock Operations Flowchart LOCKING OPERATIONS PROCEDURE Start Lock Setup Write 60 h Block Address Lock Confirm Write 01 ,D0,2Fh Block Address Read ID Plane Write 90 h Read Block Lock Status Locking No Change ? Yes ...
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Figure 45: Protection Register Programming Flowchart PROTECTION REGISTER PROGRAMMING PROCEDURE Start Write 0xC0, (Program Setup) PR Address Write PR (Confirm Data) Address & Data Read Status Register 0 SR[ Full Status Check (if desired) Program Complete FULL STATUS ...
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P30 Appendix C Common Flash Interface The Common Flash Interface (CFI) is part of an overall specification for multiple command-set and control-interface descriptions. This appendix describes the database structure containing the data returned by a read operation after issuing the ...
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Table 36: Example of Query Structure Output of x16- Devices Word Addressing: Offset Hex Code A – 00010h 0051 00011h 0052 00012h 0059 P_ID 00013h LO P_ID 00014h HI P 00015h LO P 00016h HI 00017h A_ID LO ...
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P30 Table 39: System Interface Information Offset Length 1Bh 1 1Ch 1 1Dh 1 1Eh 1 1Fh 1 20h 1 21h 1 22h 1 23h 1 24h 1 25h 1 26h 1 November 2007 Order Number: 306666-11 Description V logic ...
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C.4 Device Geometry Definition Table 40: Device Geometry Definition Offset Length 1 27h 28h 2 2 2Ah 2Ch 1 4 2Dh 4 31h 35h 4 A ddress 27: 28: 29 2B: 2C: 2D: 2E: 2F: 30: 31: 32: ...
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P30 C.5 Numonyx-Specific Extended Query Table Table 41: Primary Vendor-Specific Extended Query (1) Length Offset P = 10Ah (P+0)h 3 Primary extended query table (P+1)h Unique ASCII string “PRI“ (P+2)h (P+3)h 1 Major version number, ASCII (P+4)h 1 Minor version ...
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Table 42: Protection Register Information (1) Length Offset P = 10Ah (P+E)h 1 (P+F)h 4 (P+10)h (P+11)h (P+12)h (P+13)h 10 (P+14)h (P+15)h (P+16)h (P+17)h (P+18)h (P+19)h (P+1A)h (P+1B)h (P+1C)h Table 43: Burst Read Information (1) Length Offset P = 10Ah ...
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P30 Table 44: Partition and Erase Block Region Information (1) Offset P = 10Ah Bottom Top Number of device hardware-partition regions within the device single hardware partition device (no fields follow). x specifies the number of ...
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Table 46: Partition Region 1 Information (continued) (1) Offset P = 10Ah Bottom Top (P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information (P+2D)h (P+2D)h bits 0– y identical-size erase blks in a partition (P+2E)h ...
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P30 Table 47: Partition and Erase Block Region Information Address 64-Mbit –B 12D: --01 12E: --24 12F: --00 130: --01 131: --00 132: --11 133: --00 134: --00 135: --02 136: --03 137: --00 138: --80 139: --00 13A: --64 ...
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Table 48: CFI Link Information (1) Length Offset P = 10Ah CFI Link Field bit definitions (P+48)h 4 (P+49)h Bits 0–9 = Address offset (within 32Mbit segment) of referenced CFI table (P+4A)h Bits 10–27 = nth 32Mbit segment of referenced ...
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P30 Appendix D Additional Information Order/Document Document/Tool Number 309045 P30 Family Specification Update 308291 Schematic Review Checklist for Numonyx™ StrataFlash 300783 Using Numonyx™ Flash Memory: Asynchronous Page Mode and Synchronous Burst Mode 290667 Numonyx™ StrataFlash Migration Guide for Numonyx™ StrataFlash ...
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... RC28F128P30B85 RC28F128P30T85 PC28F128P30B85 PC28F128P30T85 Access Speed 85 ns Parameter Location B = Bottom Parameter T = Top Parameter Product Fam ily P30 = Intel StrataFlash® Embedded Memory V = 1.7 – 2 1.7 – 3.6 V CCQ 256-Mbit TE28F256P30B95 TE28F256P30T95 JS28F256P30B95 JS28F256P30T95 RC28F256P30B85 RC28F256P30T85 PC28F256P30B85 PC28F256P30T85 November 2007 Order Number: 306666-11 P30 ...
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P30 Appendix F Ordering Information for SCSP Products Figure 47: Decoder for SCSP P30 Package Designator ® Intel SCSP, leaded ® Intel SCSP, lead-free RC = 64-Ball Easy BG A, leaded P ...