A1020B

Manufacturer Part NumberA1020B
ManufacturerActel Corporation
A1020B datasheet
 


1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Page 7/24:

Pack age Ther m al C har ac t er i s ti c s

Download datasheet (163Kb)Embed
PrevNext

Pack age Ther m al C har ac t er i s ti c s

The device junction to case thermal characteristics is
jc, and the junction to ambient air characteristics is ja. The
thermal characteristics for ja are shown with two different
air flow rates. Maximum junction temperature is 150 C.
Max junction temp. C
------------------------------------------------------------------------------------------------------------------------------------------------- -
Package Type
Plastic J-Leaded Chip Carrier
Plastic Quad Flatpack
Very Thin (1.0 mm) Quad Flatpack
Ceramic Pin Grid Array
Ceramic Quad Flatpack
Gen eral Power Eq uat i on
P = [I
standby + I
active] * V
+ I
CC
CC
CC
OL
(V
– V
) * M
CC
OH
Where:
I
standby is the current flowing when no inputs or
CC
outputs are changing.
I
active is the current flowing due to CMOS switching.
CC
I
, I
are TTL sink/source currents.
OL
OH
V
, V
are TTL level output voltages.
OL
OH
N equals the number of outputs driving TTL loads to
V
.
OL
M equals the number of outputs driving TTL loads to
V
.
OH
An accurate determination of N and M is problematical
because their values depend on the family type, design
details, and on the system I/O. The power can be divided into
two components: static and active.
Static Power Component
Actel FPGAs have small static power components that result
in lower power dissipation than PALs or PLDs. By integrating
multiple PALs/PLDs into one FPGA, an even greater
reduction in board-level power dissipation can be achieved.
A sample calculation of the maximum power dissipation for
an 84-pin plastic leaded chip carrier at commercial
temperature is as follows:
Max commercial temp. C
=
ja C W
Pin Count
jc
Still Air
44
15
68
13
84
12
100
13
80
12
84
8
84
5
The power due to standby current is typically a small
component of the overall power. Standby power is calculated
* V
* N + I
*
OL
OH
below for commercial, worst case conditions.
I
CC
3 mA
1 mA
0.75 mA
0.30 mA
Active Power Component
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the
external I/O. Active power dissipation results from charging
internal
chip
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces
and load device inputs. An additional component of the active
power dissipation is the totem-pole current in CMOS
transistor pairs. The net effect can be associated with an
equivalent capacitance that can be combined with frequency
and voltage to represent active power dissipation.
A C T
1 S eri es FPG As
150 C 70 C
---------------------------------- -
=
2.2 W
37 C W
ja
ja
300 ft/min
Units
45
35
C/W
38
29
C/W
37
28
C/W
48
40
C/W
43
35
C/W
33
20
C/W
40
30
C/W
V
Power
CC
5.25 V
15.75 mW (max)
5.25 V
5.25 mW (typ)
3.60 V
2.70 mW (max)
3.30 V
0.99 mW (typ)
capacitances
of
the
interconnect,
1-289