OV2610

Manufacturer Part NumberOV2610
DescriptionColor CMOS UXGA (2.0 MPixel) Camera Chip
ManufacturerOmniVision Technologies, Inc.
OV2610 datasheet
 


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Page 17/24:

Register Set

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Register Set

Table 11
provides a list and description of the Device Control registers contained in the OV2610. The device slave addresses
for the OV2610 are 60 for write and 61 for read.
Table 11
Device Control Register List
Address
Register
Default
(Hex)
Name
(Hex)
00
GAIN
00
01
BLUE
80
02
RED
80
03
COMA
40
04
COMB
00
05
BAVG
00
06
GbAVG
00
07
GrAVG
00
Version 1.4, September 15, 2003
R/W
AGC Gain control setting
Bit[7:6]: Reserved
Bit[5:0]: Gain control gain setting
RW
• Range: 1x to 8x
Gain = (Bit[5]+1) x (Bit[4]+1) x (1+Bit[3:0]/16)
Note: Set COMI[0] = 0 to disable AGC.
Blue gain control MSB, 8 bits (LSB 2 bits in COMA[3:2] - see
on page
17).
• Range: 1/5x to 5x
RW
If BLUE[9] = 1, then Blue gain = 1 + BLUE[8:0]/128
If BLUE[9] = 0, then Blue gain = 1/(1 + BLUE_B[8:0]/128),
where BLUE_B[8:0] is the bit reverse of BLUE[8:0].
Red gain control MSB, 8 bits (LSB 2 bits in COMA[1:0] - see
on page
17).
• Range: 1/5x to 5x
RW
If RED[9] = 1, then Red gain = 1 + RED[8:0]/128
If RED[9] = 0, then Red gain = 1/(1 + RED_B[8:0]/128),
where RED_B[8:0] is the bit reverse of RED[8:0].
Common Control A
Bit[7:4]: AWB update threshold
RW
Bit[3:2]: BLUE channel lower 2 bits of Blue gain control
Bit[1:0]: RED channel lower 2 bits of Blue gain control
Common Control B
Bit[7:6]: AWB Step Selection
00: 1023 steps
01: 255 steps
10: 511 steps
11: 255 steps
RW
Bit[5:4]: AWB Update Speed Selection
00: Slow
01: Slowest
10: Fast
11: Fast
Bit[3]:
Reserved
Bit[2:0]: AEC lower 3 bits – AEC[2:0]
RW
B Channel Average
RW
G Channel Average - Picked G pixels in the same line with B pixels.
RW
G Channel Average - Picked G pixels in the same line with R pixels.
Proprietary to OmniVision Technologies

Register Set

Description
“COMA”
“COMA”
17