SAK-XC2365A-104F80L AA Infineon Technologies, SAK-XC2365A-104F80L AA Datasheet
SAK-XC2365A-104F80L AA
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SAK-XC2365A-104F80L AA Summary of contents
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Architecture XC2361A, XC2363A, XC2364A, XC2365A 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family Derivatives / Base Line Data Sheet V2.0 2009- ...
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... Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...
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Architecture XC2361A, XC2363A, XC2364A, XC2365A 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family Derivatives / Base Line Data Sheet V2.0 2009- ...
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... Debug interface timing detailled Trademarks C166™, TriCore™, and DAVE™ are trademarks of Infineon Technologies AG. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. ...
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Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pad Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Single-Chip Microcontroller with 32-Bit Performance XC236xA (XC2000 Family) 1 Summary of Features For a quick overview and easy reference, the features of the XC236xA are summarized here. • High-performance CPU with five-stage pipeline and MPU – 12.5 ns instruction ...
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Two capture/compare units for flexible PWM signal generation (CCU6x) – Two Synchronizable A/D Converters with a total channels, 10-bit resolution, conversion time below 1 μs, optional data preprocessing (data reduction, range check), broken wire detection ...
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... SAF-…: -40°C to 85°C – SAK-…: -40°C to 125°C • the package and the type of delivery. For ordering codes for the XC236xA please contact your sales representative or local distributor ...
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... Flash SAK-XC2363A- 448 Kbytes 56FxxL Flash SAF-XC2363A- 448 Kbytes 56FxxL Flash SAK-XC2361A- 448 Kbytes 56FxxL Flash SAK-XC2361A- 576 Kbytes 72FxxL Flash 1) This Data Sheet is valid for devices starting with and including design step AA placeholder for the available speed grade (in MHz). ...
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All derivatives additionally provide 8 Kbytes SBRAM, 2 Kbytes DPRAM, and 16 Kbytes DSRAM. 4) Specific information about the available channels in Analog input channels are listed for each Analog/Digital Converter module separately (ADC0 + ADC1). 1.3 Definition of ...
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General Device Information The XC236xA series (16/32-Bit Single-Chip Microcontroller with 32-Bit Performance part of the Infineon XC2000 Family of full-feature single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of ...
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Pin Configuration and Definition The pins of the XC236xA are described in detail in functions. For further explanations please refer to the footnotes at the end of the table. Figure 2 summarizes all pins, showing their locations on the ...
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Key to Pin Definitions • Ctrl.: The output signal for a port pin is selected by bitfield PC in the associated register Px_IOCRy. Output O0 is selected by setting the respective bitfield PC to 1x00 , output O1 is selected ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B EMUX1 O1 U0C1_DOUT O2 U0C0_DOUT O3 TMS_C I U0C1_DX0F St/B EXTCLK O1 BRKIN_C ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/A EMUX1 O1 T3OUT O2 U1C1_DOUT O3 ADCx_REQT I RyE RxDC2E I ESR1_6 St/A EMUX2 O1 T6OUT O2 U1C1_SCLK ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 22 P5.0 I ADC0_CH0 I 23 P5.2 I ADC0_CH2 I TDI_A I 24 P5.3 I ADC0_CH3 I T3INA I 28 P5.4 I ADC0_CH4 I T3EUDA I TMS_A I 29 P5.5 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 32 P5.10 I ADC0_CH10 I ADC1_CH10 I BRKIN_A I U2C1_DX0F I CCU61_T13 I HRA 33 P5.11 I ADC0_CH11 I ADC1_CH11 I 34 P5.13 I ADC0_CH13 I 35 P5.15 I ADC0_CH15 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B AD13 St/B RxDC0C I T5INB St/B TxDC0 O1 AD14 St/B T5EUDB I ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B TxDC2 O2 CC2_CC25 St/B CS1 OH T4EUDB I ESR1_8 St/B U0C1_DOUT O1 TxDC0 O2 CC2_CC17 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U0C0_SELO O1 0 U0C1_SELO O2 1 CC2_CC19 St/B A19 OH U0C0_DX2D I RxDC0D I ESR2_6 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U0C1_SELO O1 0 U0C0_SELO O2 1 CC2_CC20 St/B A20 OH U0C1_DX2C I RxDC1C I ESR2_7 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U0C1_DOUT O1 TxDC1 O2 CC2_CC22 St/B A22 OH CLKIN1 I TCK_A St/B U1C0_SCLK O1 OUT ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 60 P10 St/B U0C0_DOUT O1 CCU60_CC6 O2 1 AD1 St/B CCU60_CC6 I 1INA U0C0_DX1A I U0C0_DX0B St/B U1C0_SELO ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U1C1_SELO O1 0 U1C0_SELO O2 1 CCU61_COU O3 T61 A4 OH U1C1_DX2A I RxDC1B I ESR2_8 I 65 P2. St/B U2C1_SELO ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U1C1_SCLK O1 OUT U1C0_SELO O2 2 CCU61_COU O3 T62 A5 OH U1C1_DX1A I U1C0_DX1C I 69 P10 St/B U0C0_SELO O1 3 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U1C1_DOUT O1 TxDC1 O2 CCU61_COU O3 T63 A6 OH U1C1_DX0A I CCU61_CTR I APA U1C1_DX1B I 72 P10 St/B U0C0_DOUT O1 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U1C1_DOUT O1 U1C0_SELO U1C1_DX0B I CCU61_CTR I APB 78 P1 St/B U1C0_MCLK O1 OUT U1C0_SELO O2 4 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 80 P10 St/B U0C0_SELO O1 4 U0C1_MCLK O2 OUT AD9 St/B CCU60_CCP I OS2A TCK_B I T3INB St/B ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 83 P10. St/B U1C0_SCLK O1 OUT BRKOUT O2 AD11 St/B U1C0_DX1D I RxDC2B I TMS_B St/B U1C0_SELO O2 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 86 P10. St/B U1C0_DOUT O1 U1C0_SELO O3 3 WR/WRL OH U1C0_DX0D St/B U1C0_SELO O2 7 U2C0_SELO O3 4 A11 OH ESR2_4 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 91 P10. St/B U1C0_SELO O1 2 U0C1_DOUT O2 U1C0_DOUT O3 ALE OH U0C1_DX1C St/B U1C1_SELO O2 3 BRKOUT O3 A13 OH ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 97 PORST I 98 ESR1 St/B RxDC0E I U1C0_DX0F I U1C0_DX2C I U1C1_DX0C I U1C1_DX2B I U2C1_DX2C I 99 ESR0 St/B U1C0_DX0E I U1C0_DX2B ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl DDPB 25, 27, 50, 52, 75, 77, 100 26, 51 generate the reference clock output for bus timing measurement, EXTCLK ...
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Functional Description The architecture of the XC236xA combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a well-balanced design. On-chip memory blocks allow the design of compact systems-on-silicon with maximum performance suited for computing, ...
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Memory Subsystem and Organization The memory space of the XC236xA is configured in the von Neumann architecture. In this architecture all internal and external resources, including code memory, data memory, registers and I/O ports, are organized in the same ...
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Table 6 XC236xA Memory Map (cont’d) Address Area Reserved MultiCAN/USIC regs. Reserved USIC registers MultiCAN registers External memory area SFR area Dual-Port RAM Reserved for DPRAM ESFR area XSFR area Data SRAM Reserved for DSRAM External memory area 1) The ...
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Kbytes of on-chip Stand-By SRAM (SBRAM) provide storage for system-relevant user data that must be preserved while the major part of the device is powered down. The SBRAM is accessed via a specific interface and is powered in domain ...
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External Bus Controller All external memory access operations are performed by a special on-chip External Bus Controller (EBC). The EBC also controls access to resources connected to the on-chip LXBus (MultiCAN and the USIC modules). The LXBus is an ...
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Central Processing Unit (CPU) The core of the CPU consists of a 5-stage execution pipeline with a 2-stage instruction- fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing three ...
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With this hardware most XC236xA instructions can be executed in a single machine cycle of 12.5 ns with an 80-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle, no matter how many bits ...
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Memory Protection Unit (MPU) The XC236xA’s Memory Protection Unit (MPU) protects user-specified memory areas from unauthorized read, write, or instruction fetch accesses. The MPU can protect the whole address space including the peripheral area. This completes establisched mechanisms such ...
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Interrupt System With a minimum interrupt response time of 7/11 program execution), the XC236xA can react quickly to the occurrence of non- deterministic events. The architecture of the XC236xA supports several mechanisms for fast and flexible response to service ...
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Table 7 XC236xA Interrupt Nodes Source of Interrupt or PEC Service Request CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20, or USIC0 Channel 0, Request 3 CAPCOM Register 21, or USIC0 Channel 1, ...
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Table 7 XC236xA Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request A/D Converter Request 0 A/D Converter Request 1 A/D Converter Request 2 A/D Converter Request 3 A/D Converter Request 4 A/D Converter Request 5 A/D Converter Request ...
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Table 7 XC236xA Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAN Request 6 CAN Request 7 CAN Request 8 CAN Request 9 CAN Request 10 CAN Request 11 CAN Request 12 CAN Request 13 CAN Request 14 ...
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Table 7 XC236xA Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request SCU External Request 0 SCU External Request 1 SCU External Request 2 SCU Request 1 SCU Request 0 SCU External Request 3 RTC End of PEC Subchannel ...
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The XC236xA includes an excellent mechanism to identify and process exceptions or error conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware trap causes an immediate non-maskable system reaction similar to a standard interrupt service (branching to a ...
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On-Chip Debug Support (OCDS) The On-Chip Debug Support system built into the XC236xA provides a broad range of debug and emulation features. User software running on the XC236xA can be debugged within the target system environment. The OCDS is ...
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Capture/Compare Unit (CAPCOM2) The CAPCOM2 unit supports generation and control of timing sequences channels with a maximum resolution of one system clock cycle (eight cycles in staggered mode). The CAPCOM2 unit is typically used to ...
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When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘captured’) into the capture/compare register in response to an external event at the port pin associated with this register. In ...
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Capture/Compare Units CCU6x The XC236xA types feature several CCU6 units (CCU60, CCU61). The CCU6 is a high-resolution capture and compare unit with application-specific modes. It provides inputs to start the timers synchronously, an important feature in devices with several ...
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SYS TxHR T12 Interrupts st art T13 Figure 6 Mod_Name Block Diagram Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined. Timer T13 can work in compare mode only. ...
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General Purpose Timer (GPT12E) Unit The GPT12E unit is a very flexible multifunctional timer/counter structure which can be used for many different timing tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...
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T3CON.BPS1 GPT T2IN T2 Mode Control T2EUD T3 T3IN Mode Control T3EUD T4IN T4 Mode Control T4EUD Figure 7 Block Diagram of GPT1 Data Sheet XC2361A, XC2363A, XC2364A, XC2365A XC2000 Family Derivatives / Base Line Basic ...
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With its maximum resolution of 2 system clock cycles, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which ...
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T6CON.BPS2 GPT T5IN Mode T5EUD Control CAPIN CAPREL Mode Control T3IN/ T3EUD Mode T6IN Control T6EUD Figure 8 Block Diagram of GPT2 Data Sheet XC2361A, XC2363A, XC2364A, XC2365A XC2000 Family Derivatives / Base Line Basic Clock ...
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Real Time Clock The Real Time Clock (RTC) module of the XC236xA can be clocked with a clock signal selected from internal sources or external sources (pins). The RTC basically consists of a chain of divider blocks: • Selectable ...
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The RTC module can be used for different purposes: • System clock to determine the current time and date • Cyclic time-based interrupt, to provide a system time tick independent of CPU frequency and other resources • 48-bit timer for ...
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A/D Converters For analog signal measurement two 10-bit A/D converters (ADC0, ADC1) with multiplexed input channels and a sample and hold circuit have been integrated on-chip. 4 inputs can be converted by both A/D ...
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Universal Serial Interface Channel Modules (USIC) The XC236xA features several USIC modules (USIC0, USIC1, USIC2), each providing two serial communication channels. The Universal Serial Interface Channel (USIC) module is based on a generic data shift and data storage structure ...
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Target Protocols Each USIC channel can receive and transmit data frames with a selectable data word width from bits in each of the following protocols: • UART (asynchronous serial channel) – module capability: maximum baud rate = ...
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MultiCAN Module The MultiCAN module contains independently operating CAN nodes with Full-CAN functionality which are able to exchange Data and Remote Frames using a gateway function. Transmission and reception of CAN frames is handled in accordance with CAN specification ...
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MultiCAN Features • CAN functionality conforming to CAN specification V2.0 B active for each CAN node (compliant to ISO 11898) • Independent CAN nodes • Set of independent message objects (shared by the CAN nodes) • Dedicated control registers for ...
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Watchdog Timer The Watchdog Timer is one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after an application reset of the chip. ...
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Parallel Ports The XC236xA provides I/O lines which are organized into 7 input/output ports and 2 input ports. All port lines are bit-addressable, and all input/output lines can be individually (bit-wise) configured via port control registers. ...
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Instruction Set Summary Table 11 lists the instructions of the XC236xA. The addressing modes that can be used with a specific instruction, the function of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction ...
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Table 11 Instruction Set Summary (cont’d) Mnemonic Description ROL/ROR Rotate left/right direct word GPR ASHR Arithmetic (sign bit) shift right direct word GPR MOV(B) Move word (byte) data MOVBS/Z Move byte operand to word op. with sign/zero extension JMPA/I/R Jump ...
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Table 11 Instruction Set Summary (cont’d) Mnemonic Description NOP Null operation CoMUL/CoMAC Multiply (and accumulate) CoADD/CoSUB Add/Subtract Co(A)SHR (Arithmetic) Shift right CoSHL Shift left CoLOAD/STORE Load accumulator/Store MAC register CoCMP Compare CoMAX/MIN Maximum/Minimum CoABS/CoRND Absolute value/Round accumulator CoMOV Data move ...
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Electrical Parameters The operating range for the XC236xA is defined by its electrical parameters. For proper operation the specified limits must be respected during system design 4.1 General Parameters These parameters are valid for all subsequent descriptions, unless otherwise ...
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Operating Conditions The following operating conditions must not be exceeded to ensure correct operation of the XC236xA. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Note: Typical parameter values refer to room temperature ...
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Table 13 Operating Condition Parameters (cont’d) Parameter Absolute sum of overload currents External Pin Load Capacitance Voltage Regulator Buffer Capacitance for DMP_M Voltage Regulator Buffer Capacitance for DMP_1 Operating frequency Ambient temperature 1) Performance of pad drivers, A/D Converter, and ...
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CC (Controller Characteristics): The logic of the XC236xA provides signals with the specified characteristics. SR (System Requirement): The external system must provide signals with the specified characteristics to the XC236xA. Data Sheet XC2361A, XC2363A, XC2364A, XC2365A XC2000 Family Derivatives / ...
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DC Parameters These parameters are static or average values that may be exceeded during switching transitions (e.g. output current). The XC236xA can operate within a wide supply voltage range from 3 5.5 V. However, during operation this ...
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Pullup/Pulldown Device Behavior Most pins of the XC236xA feature pullup or pulldown devices. For some special pins these are fixed; for the port pins they can be selected by the application. The specified current values indicate how to load the ...
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DC Parameters for Upper Voltage Area These parameters apply to the upper IO voltage range, 4.5 V ≤ Note: Operating Conditions apply. Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal ...
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Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot suppress switching due to external system noise under all conditions. 2) The maximum deliverable ...
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DC Parameters for Lower Voltage Area These parameters apply to the lower IO voltage range, 3.0 V ≤ Note: Operating Conditions apply. Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal ...
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Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot suppress switching due to external system noise under all conditions. 2) The maximum deliverable ...
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Power Consumption The power consumed by the XC236xA depends on several factors such as supply voltage, operating frequency, active circuits, and operating temperature. The power consumption specified here consists of two components: • The switching current I • The ...
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A small current is consumed because the drivers’ input stages are switched. 2) Please consider the additional conditions described in section “Active Mode Power Supply ...
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I [mA] S 100 Figure 13 Supply Current in Active Mode as a Function of Frequency Note: Operating Conditions apply. Data Sheet XC2361A, XC2363A, XC2364A, XC2365A XC2000 Family Derivatives / ...
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Table 17 Leakage Power Consumption XC236xA Parameter 2) Leakage supply current 3) : 600,000 × e -α Formula ; α = 5000 / (273 + B× Typ 1.0, Max 1.3 1) All inputs ...
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I [mA -50 Figure 14 Leakage Supply Current as a Function of Temperature Data Sheet XC2361A, XC2363A, XC2364A, XC2365A XC2000 Family Derivatives / Base Line 0 50 100 84 Electrical Parameters I ...
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Analog/Digital Converter Parameters These parameters describe the conditions for optimum ADC performance. Note: Operating Conditions apply. Table 18 A/D Converter Characteristics Parameter Analog reference supply Analog reference ground Analog input voltage range Analog clock frequency Conversion time for 10-bit ...
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Table 18 A/D Converter Characteristics (cont’d) Parameter Total capacitance of an analog input Switched capacitance of an analog input Resistance of the analog input path Total capacitance of the reference input Switched capacitance of the reference input Resistance of the ...
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R Source V AIN Figure 15 Equivalent Circuitry for Analog Inputs Data Sheet XC2361A, XC2363A, XC2364A, XC2365A XC2000 Family Derivatives / Base Line R AIN Ext AINT AINS 87 Electrical Parameters A/D Converter C AINS ...
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Sample time and conversion time of the XC236xA’s A/D converters are programmable. The timing above can be calculated using f The limit values for must not be exceeded when selecting the prescaler value. ADCI Table 19 A/D Converter Computation Table ...
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System Parameters The following parameters specify several aspects which are important when integrating the XC236xA into an application system. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 20 Various System Parameters ...
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Table 21 Coding of Bitfields LEVxV in Register SWDCON0 Code Default Voltage Level 0000 2 0001 3 0010 3 0011 3 0100 3 0101 3 0110 3.6 V ...
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Flash Memory Parameters The XC236xA is delivered with all Flash sectors erased and with no protection installed. The data retention time of the XC236xA’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on ...
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Access to the XC236xA Flash modules is controlled by the IMB. Built-in prefetch mechanisms optimize the performance for sequential access. Flash access waitstates only affect non-sequential access. Due to prefetch mechanisms, the performance for sequential access (depending on the software ...
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AC Parameters These parameters describe the dynamic behavior of the XC236xA. 4.6.1 Testing Waveforms These values are used for characterization and production testing (except pin XTAL1). Output delay Hold time 0.8 V DDP 0.7 V DDP 0.3 V DDP ...
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Definition of Internal Timing The internal operation of the XC236xA is controlled by the internal system clock Because the system clock signal external sources using different mechanisms, the duration of the system clock periods (TCSs) and their variation (as ...
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Direct Drive When direct drive operation is selected (SYSCON0.CLKSEL = 11 derived directly from the input clock signal CLKIN1 SYS IN f The frequency of is the same as the frequency of SYS f times of ...
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The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the minimum TCS possible under the given circumstances. The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is constantly ...
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D Acc. jitter T ns ±9 ±8 ±7 ±6 ±5 ±4 ±3 ±2 ± Figure 19 Approximated Accumulated PLL Jitter Note: The specified PLL jitter values are valid if the capacitive load per pin does not C ...
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Wakeup Clock When wakeup operation is selected (SYSCON0.CLKSEL = 00 derived from the low-frequency wakeup clock source SYS WU In this mode, a basic functionality can be maintained without requiring an external clock source and while ...
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External Clock Input Parameters These parameters specify the external clock generation for the XC236xA. The clock can be generated in two ways: • By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2. • By supplying an external clock ...
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V OFF Figure 20 External Clock Drive XTAL1 Note: For crystal/resonator operation strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimum parameters for oscillator operation. Please refer to ...
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Pad Properties The output pad drivers of the XC236xA can operate in several user-selectable modes. Strong driver mode allows controlling external components requiring higher currents such as power bridges or LEDs. Reducing the driving power of an output pad ...
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Table 28 Standard Pad Parameters (Lower Voltage Range) Parameter 1) Maximum output current Nominal output current Rise/Fall time (10%-90%) Valid for external capacitances in the range ≤ ≤ 100 [pF]) L ...
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External Bus Timing The following parameters specify the behavior of the XC236xA bus interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 29 CLKOUT Reference Signal Parameter CLKOUT cycle time CLKOUT ...
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Variable Memory Cycles External bus cycles of the XC236xA are executed in five consecutive cycle phases (AB F). The duration of each cycle phase is programmable (via the TCONCSx registers) to adapt the external bus cycles to ...
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Table 31 External Bus Cycle Timing for Upper Voltage Range Parameter Output valid delay for: RD, WR(L/H) Output valid delay for: BHE, ALE Address output valid delay for: A23 … A16, A15 … A0 Address output valid delay for: AD15 ...
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Table 32 External Bus Cycle Timing for Lower Voltage Range Parameter Output valid delay for: RD, WR(L/H) Output valid delay for: BHE, ALE Address output valid delay for: A23 … A16, A15 … A0 Address output valid delay for: AD15 ...
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CLKOUT t 11 ALE A23-A16, BHE, CSx RD WR(L/H) t AD15-AD0 (read) t AD15-AD0 (write) Figure 22 Multiplexed Bus Cycle Data Sheet XC2361A, XC2363A, XC2364A, XC2365A XC2000 Family Derivatives / Base Line ...
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AB CLKOUT t 11 ALE A23-A0, BHE, CSx RD WR(L/H) D15-D0 (read) D15-D0 (write) Figure 23 Demultiplexed Bus Cycle Data Sheet XC2361A, XC2363A, XC2364A, XC2365A XC2000 Family Derivatives / Base Line ...
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Bus Cycle Control with the READY Input The duration of an external bus cycle can be controlled by the external circuit using the READY input signal. The polarity of this input signal can be selected. Synchronous READY permits the shortest ...
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CLKOUT RD, WR D15-D0 (read) D15-D0 (write) READY Synchronous READY Asynchron. Figure 24 READY Timing Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”) a READY-controlled waitstate is inserted (tpRDY), sampling the READY input ...
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Synchronous Serial Interface Timing The following parameters are applicable for a USIC channel operated in SSC mode. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table 33 SSC ...
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Table 34 SSC Master/Slave Mode Timing for Lower Voltage Range Parameter Master Mode Timing Slave select output SELO active to first SCLKOUT transmit edge Slave select output SELO inactive after last SCLKOUT receive edge Transmit data output valid time Receive ...
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Master Mode Timing Select Output Inactive SELOx Clock Output SCLKOUT Data Output DOUT Data Input DX0 Slave Mode Timing Select Input Inactive DX2 Clock Input DX1 Data Input DX0 Data Output DOUT Transmit Edge: with this clock edge , transmit ...
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Debug Interface Timing The debugger can communicate with the XC236xA either via the 2-pin DAP interface or via the standard JTAG interface. Debug via JTAG The following parameters are applicable for communication through the JTAG debug interface. The JTAG ...
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Table 36 JTAG Interface Timing Parameters for Lower Voltage Range Parameter TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time TDI/TMS setup to TCK rising edge TDI/TMS hold after TCK rising edge ...
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TCK TMS TDI t 9 TDO Figure 27 JTAG Timing Data Sheet XC2361A, XC2363A, XC2364A, XC2365A XC2000 Family Derivatives / Base Line Electrical Parameters 116 t 10 MC_JTAG ...
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Debug via DAP The following parameters are applicable for communication through the DAP debug interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table 37 DAP Interface Timing Parameters ...
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Table 38 DAP Interface Timing Parameters for Lower Voltage Range Parameter DAP0 clock period DAP0 high time DAP0 low time DAP0 clock rise time DAP0 clock fall time DAP1 setup to DAP0 rising edge DAP1 hold after DAP0 rising edge ...
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DAP0 DAP1 Figure 29 Data Transfer Timing Host to Device (DAP1) DAP1 Figure 30 Data Transfer Timing Device to Host (DAP1) Note: The transmission timing is determined by the receiving debugger by evaluating the sync-request synchronization pattern telegram. Data Sheet ...
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Package and Reliability In addition to the electrical parameters, the following specifications ensure proper integration of the XC236xA into the target system. 5.1 Packaging These parameters specify the packaging rather than the silicon. Table 39 Package Parameters (PG-LQFP-100-8) Parameter ...
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Package Outlines 0.5 12 0.22 ±0.05 0. 100 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side Figure 31 PG-LQFP-100-8 (Plastic Green Thin Quad Flat Package) All dimensions ...
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Thermal Considerations When operating the XC236xA in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage. The maximum heat that can be dissipated depends ...
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... Published by Infineon Technologies AG B158-H9272-G3-X-7600 ...