AT8989UP Atan Technology, AT8989UP Datasheet
AT8989UP
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AT8989UP Summary of contents
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... ATAN Technology, Inc. AT8989UP 9 port 10/100 Mb/s Single Chip Ethernet Switch Controller Preliminary Data Sheet Revision 1.1 Feb 2002 9 port 10/100Mb/s Single Chip Switch Controller 1 Revision 1.1 AT8989UP ...
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... TXER power on latch Dual Speed mode each port support 100/10 Full/Half Separate Data Sheet from AT8989P 0.4 1. Remove PHY Register from Data Sheet 2. Add AT8989UP 16 port application note in 3.5 0.9 3. Add EEPROM read explain in Dupcol1 pin. 4. Modify LED display pin description. 1. ...
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... Full-Duplex mode to prevent packet lost when buffer full. When Back Pressure is enabled, and there is no receive buffer available for the incoming packet, the AT8989UP will issue a JAM pattern on the receiving port in Half Duplex mode and transmit the 802.3x Pause packet back to receiving end in Full Duplex mode. ...
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... QFP package with 2.25V/3.3V power supply. 1.3 Applications AT8989UP in 208-pin PQFP 10/100 MDIX TX/FX + FX/CPU Port. B. 16-port Smart Switch with two AT8989UPs by 1.6Gbps Expansion bus, - Any group of port-base VLAN, Trunking with console port. AT8989UP 8 10/100 MDIX TX/FX 9 port 10/100Mb/s Single Chip Switch Controller ...
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... GTXD7 85 GNDO 84 GNDO 83 LDSPD7 82 LDSPD6 81 LDSPD5 80 (SPD_P7) LDSPD4 79 GNDO 78 GNDO 77 VCC3O 76 VCC3O 75 (SPD_P6) LDSPD3 74 (SPD_P4) LDSPD2 73 VCC2IK 72 VCC2IK 71 GNDIK 70 GNDIK 69 (SPD_P2) LDSPD1 68 (SPD_P0) LDSPD0 67 CFG1 66 TEST 65 VCC2IK 64 VCC2IK 63 GNDIK 62 GNDIK 61 GNDSUBA 60 VCCA2 59 TXP7 58 TXN7 57 GNDA 56 GNDA 55 RXP7 54 RXN7 53 VCCAD Revision 1.1 AT8989UP ...
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... Power-on-reset, Signals latched as TX (“0”), FX(“1”) mode at Port7. PD Internal pull down as Port7 TX mode. I Expansion Port Receive Data bit During power on reset, GRXD0 value will be latched by AT8989UP at the rising edge of RESETL for TSEL0. Internal pull down. 6 SCHE: Schmitt Trigger 2.25V/3V: 2.25V with 3.3V tolerance Pin Description Revision 1 ...
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... PD latched by AT8989UP at the rising edge of RESETL for TSEL2. Internal pull down I, Expansion/MII Port Carrier Sense During power on reset, GCRS value PD will be latched by AT8989UP at the rising edge of RESETL for TSEL1. Internal pull down O Expansion Port clock Output 16mA I Expansion Port or MII Port Receive Clock Input ...
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... Analog Analog Reference Voltage Input For Power On reset. SCHE I, 25M Crystal Input. 25M Crystal Input. Variation is limited to +/- Analog 50ppm. O, 25M Crystal Output. When connected to oscillator, this pin should left Analog unconnected. I, TTL Must connect to Ground. Power/Ground., 98 pins 8 “0” to enable MDIX. Revision 1.1 AT8989UP ...
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... Power Used by Digital Core Ground Used by Digital Pad 3.3V, Power Used by Digital Pad. 3.3V, Power used of Regulator Ground used of Regulator I, Scan Enable. This pin will be used as the scan enable input for testing. TTL Connect to GND at normal application. NC pin., 12 pins Not Connect. 9 Revision 1.1 AT8989UP ...
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... The 100Base-X receiver consists of functional blocks required to recover and condition the 125 Mbps receive data stream. The AT8989UP implements the 100Base-X receiving state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125 Mbps receive data stream may originate from the on-chip twisted-pair transceiver in a 100Base-TX application ...
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... Symbol Alignment The symbol alignment circuit in the AT8989UP determines code word alignment by recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the de-scrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. ...
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... A bad start of stream delimiter (Bad SSD error condition that occurs in the 100Base-X receiver if carrier is detected (CRS asserted) and a valid /J/K set of code-group (SSD) is not received. If this condition is detected, then the AT8989UP will assert RXER and present RXD[3:0] = 1110 to the internal MII for the 9 port 10/100Mb/s Single Chip Switch Controller 12 Revision 1 ...
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... The AT8989UP uses an adaptive equalizer that changes filter frequency response in accordance with cable length. The cable length is estimated based on the incoming signal strength. The equalizer tunes itself automatically for any cable length to compensate for the amplitude and phase distortions incurred from the cable ...
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... Within one and half bit times after the last bit, carrier sense is de-asserted. 3.2.4.3 Transmit Driver and Receiver The AT8989UP integrates all the required signal conditioning functions in its 10Base-T block such that external filters are not required. Only one isolation transformer and impedance matching resistors are needed for the 10Base-T transmit and receive interface ...
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... AMC via the RMII. 3.2.7 Jabber Function The jabber function monitors the AT8989UP output and disables the transmitter if it attempts to transmit a longer than legal sized packet. If TXEN is high for greater than 24ms, the 10Base-T transmitter will be disabled. Once disabled by the jabber function, the transmitter stays disabled for the entire time that the TXEN signal is asserted ...
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... If the port number is equal to the port on which the packet was received, the packet is discarded. If the port number is different, the packet is forwarded across the bridge. (2) If the UNICAST address and the address was not found, the AT8989UP treats multicast packet and forwards across the bridge. ...
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... Full Duplex Flow Control When full duplex port run out of its receive buffer, a PAUSE packet command will be issued by AT8989UP to notice the packet sender to pause transmission. This frame based flow control is totally compliant to IEEE 802.3x. AT8989UP can issue or receive pause packet ...
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... Port locking function will provide customer simple way to limit per port user number to one. If this function is turn on then AT8989UP will lock first MAC address in learning table. After this MAC address locking will never age out except Reset signal. Another MAC address which not same as locking one will be dropped. AT8989UP provide one MAC address per port ...
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... AT8989UP is designed as 256bytes/block of internal memory. The packets with less 256 bytes length will occupy one block. And AT8989UP will link 2~6 blocks to store the packets of more then 256bytes. This buffer management will provide a better memory utilization on the limited memory size and get a better performance on the real network application ...
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... AT8989UP provides eight ports 100/10 Half/Full port plus one expansion bus with bandwidth up to 1.6Gbps. Two AT8989UPs can connect each other with the expansion bus 16-port wire-speed Switching Hub. The expansion bus is implemented by the existing GMII interface at 100Mhz. Such configuration could get good result at both of Novell’s Performance test and the HOL on smart-bit AST, even though it will increase latency around 12% across chips ...
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... VLAN 15 outbound Port Map P0 Buffer Threshold P2 Buffer Threshold P4 Buffer Threshold P6 Buffer Threshold P8 Buffer Threshold Description 21 0h 8000h fa50h fa50h fa50h fa50h aa40h ff00h 3600h 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh 1ffh Revision 1.1 AT8989UP ...
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... Crossover auto-detect enable Description Reserve Reserve Enable Replace VLAN ID 0 &1 by PVID Reserved Description Port 0~7 MII Register Address Port 0~7 MII Write Enable. High Active Enable IPG leveling Enable Trunk Port Port 8 MII Register Address Port 8 MII Write Enable. High Active 22 Revision 1.1 AT8989UP ...
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... Mapped priority of tag value(VLAN, TOS) 3 Mapped priority of tag value(VLAN, TOS) 4 Mapped priority of tag value(VLAN, TOS) 5 Mapped priority of tag value(VLAN, TOS) 6 Mapped priority of tag value(VLAN, TOS) 7 Description Broadcast Storming Threshold[1:0] Broadcast Storming Enable Reserve XCRC (0/XCRCCHK, enable CRC Check) Reserve 23 Revision 1.1 AT8989UP ...
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... Reserve Reserve Power Saving Select Recommend LED variety Lnkact 00 Single color 01 Single color 10 Dual color 11 Dual color Description VLAN mapping table. Description 24 Dupcol Speed (always single color) Single color Duplex/col Single color duplex Dual color Duplex/col Dual color duplex Revision 1.1 AT8989UP ...
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... Bit [13:8], Bit [5:0] Total Buffer Threshold: 0x27h Configuration Bit [5:0] Bit 7 9 port 10/100Mb/s Single Chip Switch Controller Port Buffer Threshold (available buffers are 8 times of the value) Description Total Buffer Threshold for all ports 1: Enable EEPROM Threshold value, 0: default Threshold value 25 Revision 1.1 AT8989UP ...
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... Register 0x0ah: Configuration register. Bit[7~0]: Reserve. Bit 8: Reserve. Bit 9: To replace VLAN ID 0 & PVID. If this bit enable then AT8989UP will check VLAN ID. If this VLAN then AT8989UP will replace this ID by PVID. Bit[15~10]: Reserved. Register 0x0bh: Custom MII Address Register Bit[4~0]: Reserve ...
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... Bit 5: VLAN mode select, default is “0”. “0”, By-pass mode with port-base VLAN. “1”, VLAN ID base VLAN. Bit [15:6] : Reserve value “1”, Bit [4:0] : Reserve value “0”. 9 port 10/100Mb/s Single Chip Switch Controller 0: Disable. 1: Enable. 1: Disable. 0: Enable. 0: Disable. 1: Disable. 0: Enable. 27 Revision 1.1 AT8989UP ...
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... Bit[15:13]: User Priority 7~0 Bit 12: Canonical Format Indicator (CFI) Bit[11~0]: VLAN ID. The AT8989UP will use bit[3:0] as VLAN group. TOS IP Packet AT8989UP check byte 12 &13 if this value is 0800h then AT8989UP knows this is a TOP priority packet. 9 port 10/100Mb/s Single Chip Switch Controller 1: Enable. 0: Disable. ...
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... If there is any Protection instruction before or after the EEPROM WRITE instruction, CPU needs to generate a separated CS signal cycle for each Protection & WRITE instruction. CPU can directly program AT8989UP after 30ms of Reset signal rising edge with or without the presence of EEPROM. 9 port 10/100Mb/s Single Chip Switch Controller ...
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... Min Typ 3.135 3.3 2.25 2. Conditions Min Typ CMOS CMOS 0.7 * Vcc CMOS CMOS 0.7 * Vcc V =0V or 100 Vcc IH 30 Units 0 °C W °C V Max Units 3.465 Vcc V W °C Max Units 0.3 * Vcc KΩ Revision 1.1 AT8989UP ...
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... Parameter T20 Data Valid Delay after Rising GTXCLK GTXCLK Freq/125MHz, Period/8+- 0.5ns, GTXCLK high/2.5ns min, GTXCLK low/2.5ns min 9 port 10/100Mb/s Single Chip Switch Controller T10 T10 T11 Min Max Units 4 2 T20 Min Max Units 1 Revision 1.1 AT8989UP ...
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... EECS to EESK setup time T61 EDI to EESK setup time T62 EDI to EESK hold time 6.4 Expansion bus 1.6G Receive Signals Timing GRXCLK GRXD[7::0], GRXDV 9 port 10/100Mb/s Single Chip Switch Controller T60 T62 T61 Min Max Units T10 T10 T11 32 Revision 1.1 AT8989UP ...
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... RXCLK RXD[3::0], RXDV Name Parameter T10 Setup Time to Rising RXCLK T11 Hold Time to Rising RXCLK 9 port 10/100Mb/s Single Chip Switch Controller Min Max Units 4 2 T20 Min Max Units 1.5 4 T10 T10 T11 Min Max Units Revision 1.1 AT8989UP ...
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... Transmit Enable Hold Time to TXC Rising T32 Transmit Data Setup Time to TXC Rising T33 Transmit Data Hold Time to TXC Rising 9 port 10/100Mb/s Single Chip Switch Controller T20 Min 3 T30 T32 T33 Min Max Units 10 ns T31 Max Units Revision 1.1 AT8989UP ...
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... GPSI (7 wires) Receive Signals Timing RXC CRS RXD0 Name Parameter T40 Receive Data Setup Time to RXC Rising T41 Receive Data Hold Time to RXC Rising 9 port 10/100Mb/s Single Chip Switch Controller T40 T41 Min Extra Clocks Max Units ns ns Revision 1.1 AT8989UP ...
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... ATAN Technology, Inc. 7. Package 208 Pin PQFP Outside Dimension 9 port 10/100Mb/s Single Chip Switch Controller 36 Revision 1.1 AT8989UP ...
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... ATAN Technology, Inc. 9 port 10/100Mb/s Single Chip Switch Controller 37 Revision 1.1 AT8989UP ...