M12L64164A-7T Elite Semiconductor Memory Technology Inc, M12L64164A-7T Datasheet
M12L64164A-7T
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M12L64164A-7T Summary of contents
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... Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. PIN ASSIGNMENT Elite Semiconductor Memory Technology Inc. ORDERING INFORMATION 54 Pin TSOP (Type II) (400mil x 875mil ) PRODUCT NO. M12L64164A-6T M12L64164A-7T Top View ...
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... Data inputs / outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. M12L64164A L(U)DQM DQ Publication Date: Oct. 2003 Revision: 1.9 ...
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... ≤ 10ns acceptable. ≤ 10ns acceptable 0.3V, all other pins are not under test = 0V. DD ≤ OUT DD ° 1MHZ) SYMBOL C IN1 C IN2 C OUT M12L64164A VALUE UNIT -1.0 ~ 4.6 V -1.0 ~ 4.6 V ° C -55 ~ +150 ° ) MAX UNIT ...
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... CKE ≥ CLK V , tcc = IH(min) IL(max) input signals are stable mA, Page Burst, All Bank active OL Burst Length = 4, CAS Latency = 3 ≥ tcc(min) RC RC(min) CC ≤ CKE 0.2V M12L64164A VERSION UNIT NOTE -6 -7 110 100 mA 1 ...
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... RAS(max RC(min RFC(min CDL(min RDL(min BDL(min CCD(min after self refresh exit. RFC M12L64164A ° ) UNIT Vtt = 1.4V Ω 50 Ω Z0 =50 50pF (Fig Output Load Circuit UNIT NOTE - ...
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... Elite Semiconductor Memory Technology Inc. -6 SYMBOL MIN MAX 5.5 t SAC 6 2 2 SLZ 5.5 t SHZ 6 M12L64164A -7 UNIT NOTE MIN MAX 1 2 Publication Date: Oct. 2003 Revision: 1 ...
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... M12L64164A-6T CAS Frequency Latency 166 MHz (6.0ns) 3 143 MHz (7.0ns) 3 133 MHZ(7.5ns ) 3 125 MHZ(8.0ns ) 2 100 MHZ(10.0ns ) 2 M12L64164A-7T CAS Frequency Latency 143 MHZ(7.0ns ) 3 133 MHZ(7.5ns ) 3 125 MHZ(8.0ns ) 3 100 MHZ(10.0ns ) 2 83 MHZ(12.0ns ) 2 Elite Semiconductor Memory Technology Inc. ...
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... X X Exit Entry Exit Valid , X = Don’t Care Logic High , L = Logic Low ) M12L64164A DQM A13 WE A10/AP A9~A0 A12 CODE Row Address L Column ...
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... Reserved Reserved Reserved Reserved Reserved Reserved M12L64164A Burst Length Burst Length Type Sequential Interleave Reserved Reserved ...
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... M12L64164A Interleave Interleave ...
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... A10/AP~A11 and A13~A12. The write burst length is programmed using A9. A7~A8, A10/AP~A11 and A13~A12 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies. Publication Date: Oct. 2003 Revision: 1.9 M12L64164A 11/44 ...
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... Entry to power-down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state. M12L64164A after the last data input to RDL is defined as the minimum number of clock RP ...
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... The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP’s for a minimum time of t RAS reaches idle state to begin normal operation. with clock cycle RFC M12L64164A before the SDRAM RFC Publication Date: Oct. 2003 Revision: 1.9 13/44 ...
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... RAS CAS WE = Low) The M12L64164A has a mode register that defines how the device operates. In this command, A0 through A13 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2CLK (t ) following this command, the M12L64164A cannot accept any other commands ...
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... Before executing CBR refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During t period (from refresh command to refresh or activate command), the RC M12L64164A cannot accept any other command. Elite Semiconductor Memory Technology Inc. M12L64164A CLK H CKE ...
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... CS , RAS , CAS , CKE = Low , WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes to high, the M12L64164A exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. ...
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... D Q Elite Semiconductor Memory Technology Inc M12L64164A D 3 Publication Date: Oct. 2003 Revision: 1.9 19/44 ...
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... M12L64164A Publication Date: Oct. 2003 Revision: 1.9 20/44 ...
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... determinates the last data write. RDL min delay) with DQM. RAS M12L64164A * ...
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... from self refresh exit command, any other command can not be accepted. M12L64164A Publication Date: Oct. 2003 Revision: 1.9 23/44 ...
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... During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued. M12L64164A Publication Date: Oct. 2003 Revision: 1.9 24/44 ...
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... NOP (Continue Burst to End ILLEGAL X BA CA, A10/AP ILLEGAL X BA RA, RA10 ILLEGAL ILLEGAL M12L64164A ACTION Row Active) Row Active) Row active Row Active) Row Active) Row active Row Active) Row Active) Row Active) Row Active) Publication Date: Oct. 2003 Revision: 1.9 Note 2 2 ...
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... ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address M12L64164A ACTION Idle after tRP Idle after tRP Idle after tRPL Row Active after tRCD Row Active after tRCD Idle after tRFC Idle after tRFC Idle after 2clocks Idle after 2clocks AP = Auto Precharge Publication Date: Oct ...
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... X X Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend must be satisfy before any command other than exit. SS M12L64164A ACTION Note Idle after tRFC (ABI) 6 Idle after tRFC (ABI) 6 ABI 7 ABI Publication Date: Oct ...
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... *Note M12L64164A *Note2,3 *Note4 *Note2 *Note 3 *Note4 ...
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... Enable auto precharge , precharge bank B at end of burst. 0 Enable auto precharge , precharge bank C at end of burst. 1 Enable auto precharge , precharge bank D at end of burst. Precharge 0 Bank A 1 Bank B 0 Bank C 1 Bank D X All Banks M12L64164A Publication Date: Oct. 2003 Revision: 1.9 29/44 ...
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... Elite Semiconductor Memory Technology Inc M12L64164A ...
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... RC *Note2 Qa2 Qa0 Qa1 Qa3 Qa0 Qa1 Qa2 Qa3 Precharge Row Active (A- Ban k) M12L64164A Cb0 Rb Rb Db0 Db1 Db2 *Note3 Db2 Db0 Db1 *Note3 W r ite (A- Bank) (A- Ban k) ) after the clock. ...
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... Read ( A - Bank ) ( A - Bank ) before row precharge , will be written. RDL M12L64164A ...
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... Precharge (A-Bank) Row Active (D-Bank) M12L64164A ...
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... Read with Auto Precharge ( A - Bank ) Auto Precharge Start Point before internal precharge start. RAS M12L64164A ...
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... M12L64164A Publication Date: Oct ...
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... prior to Row active command. SS M12L64164A ...
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... required before exit from self refresh. RAS M12L64164A Publication Date: Oct ...
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... Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Auto Refresh Cycle M12L64164A ...
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... D 22.22 BSC E 11.76 BSC 10.16 BSC L 0.40 0.50 0.60 0.016 0.020 0.024 0.80 REF e 0.80 BSC 0° 10° Θ M12L64164A SEE DETAIL 0.21 REF 0.665 REF A 1 -C- DETAIL "A" SECTION B-B Dimension in inch Min Norm Max 0.047 0.018 0.008 ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M12L64164A Publication Date: Oct. 2003 Revision: 1.9 44/44 ...