21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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Page 127/164:

Subsystem ID Register Offset

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15.1.29
Subsystem ID Register—Offset 36h
This section describes the subsystem ID register.
Dword address = 34h
Byte enable p_cbe_l<3:0> = 00xxb
Dword Bit
31:16
Subsystem ID
15.1.30
Interrupt Pin Register—Offset 3Dh
This section describes the interrupt pin register.
Dword address = 3Ch
Byte enable p_cbe_l<3:0> = xx0xb
Dword Bit
15:8
Interrupt pin
15.1.31
Bridge Control Register—Offset 3Eh
This section describes the bridge control register.
This register must be initialized by configuration software.
Dword address = 3Ch
Byte enable p_cbe_l<3:0>= 00xxb
Dword Bit
16
Parity error response
Preliminary
Datasheet
Name
R/W
Provides a mechanism allowing add-in cards to
distinguish their cards from one another. The
21150 provides a writable subsystem ID that
R/W
can be initialized during POST. This register is
only implemented in the 21150-AA.
Reset to 0.
Name
R/W
Reads as 0 to indicate that the 21150 does not
R
have an interrupt pin.
Name
R/W
Controls the 21150’s response when a parity
error is detected on the secondary interface.
When 0—The 21150 does not assert s_perr_l,
nor does it set the data parity reported bit in the
secondary status register. The 21150 does not
report address parity errors by asserting
p_serr_l.
When 1—The 21150 drives s_perr_l and
R/W
conditionally sets the data parity reported bit in
the secondary status register when a data
parity error is detected on the secondary
interface (see
Also must be set to 1 to allow p_serr_l
assertion when address parity errors are
detected on the secondary interface.
Reset value: 0.
21150
Description
Description
Description
Section
7.0).
119