21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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Downstream Delayed Write Transaction

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21150
Figure 7. Downstream Delayed Write Transaction
CY0
Cycle
< 15ns >
p_clk
p_ad
p_cbe_l
p_frame_l
p_irdy_l
p_devsel_l
p_trdy_l
p_stop_l
s_clk
s_ad
s_cbe_l
s_frame_l
s_irdy_l
s_devsel_l
s_trdy_l
s_stop_l
The 21150 implements a discard timer that starts counting when the delayed write completion is at
the head of the delayed transaction queue. The initial value of this timer can be set to one of two
values, selectable through both the primary and secondary master timeout bits in the bridge control
register. If the initiator does not repeat the delayed write transaction before the discard timer
expires, the 21150 discards the delayed write transaction from the delayed transaction queue. The
21150 also conditionally asserts p_serr_l (see
4.5.4
Write Transaction Address Boundaries
The 21150 imposes internal address boundaries when accepting write data. The aligned address
boundaries are used to prevent the 21150 from continuing a transaction over a device address
boundary and to provide an upper limit on maximum latency. The 21150 returns a target disconnect
to the initiator when it reaches the aligned address boundaries under the conditions shown in
17.
34
CY2
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CY6
CY1
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Addr
Data
Addr
3
Byte Enables
3
Byte Enables
Addr
Data
3
Byte Enables
Section
7.4).
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Data
Addr
Data
3
Byte Enables
LJ-04844.AI4
Preliminary
Datasheet
CY14
Table